LMP90100MHX/NOPB >
LMP90100MHX/NOPB
Texas Instruments
IC AFE 1 CHAN 24BIT 28HTSSOP
2246 Pcs New Original In Stock
1 Channel AFE 24 Bit 28-HTSSOP
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LMP90100MHX/NOPB Texas Instruments
5.0 / 5.0 - (85 Ratings)

LMP90100MHX/NOPB

Product Overview

1301109

DiGi Electronics Part Number

LMP90100MHX/NOPB-DG

Manufacturer

Texas Instruments
LMP90100MHX/NOPB

Description

IC AFE 1 CHAN 24BIT 28HTSSOP

Inventory

2246 Pcs New Original In Stock
1 Channel AFE 24 Bit 28-HTSSOP
Quantity
Minimum 1

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LMP90100MHX/NOPB Technical Specifications

Category Data Acquisition, Analog Front End (AFE)

Manufacturer Texas Instruments

Packaging -

Series -

Product Status Active

Number of Bits 24

Number of Channels 1

Voltage - Supply, Analog 2.85V ~ 5.5V

Voltage - Supply, Digital 2.7V ~ 5.5V

Mounting Type Surface Mount

Package / Case 28-PowerTSSOP (0.173", 4.40mm Width)

Supplier Device Package 28-HTSSOP

Base Product Number LMP90100

Datasheet & Documents

Manufacturer Product Page

LMP90100MHX/NOPB Specifications

HTML Datasheet

LMP90100MHX/NOPB-DG

Environmental & Export Classification

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 3 (168 Hours)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001

Additional Information

Other Names
LMP90100MHX/NOPB-DG
296-51349-1
296-51349-2
296-51349-6
Standard Package
2,500

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5.0/5.0-(Show up to 5 Ratings)
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de desembre 02, 2025
5.0
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de desembre 02, 2025
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de desembre 02, 2025
5.0
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de desembre 02, 2025
5.0
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de desembre 02, 2025
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de desembre 02, 2025
5.0
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Frequently Asked Questions (FAQ)

What are the key design-in considerations when integrating the LMP90100MHX/NOPB into a low-power sensor interface for battery-operated systems?

When designing the LMP90100MHX/NOPB into battery-powered applications, a critical consideration is managing its analog supply current across temperature and sampling rates. While the device supports wide supply ranges (2.85V to 5.5V analog), current consumption can increase significantly at higher output data rates (ODR) or lower temperatures due to internal PGA and reference buffer behavior. To optimize power, use duty-cycling via the low-power mode and ensure the external reference is low-quiescent-current. Also, bypass the REFIN and AIN pins properly—TI recommends 100nF ceramic + 1μF X7R near the PCB to prevent noise coupling from affecting signal integrity, especially when measuring high-impedance sensors like bridge transducers. Avoid floating inputs; tie unused IN+ and IN− to AVSS through 10kΩ resistors to prevent latch-up or EMI issues in noisy environments.

Can the LMP90100MHX/NOPB replace the AD7124-4 in a precision weigh scale design, and what circuit modifications are needed?

The LMP90100MHX/NOPB can replace the AD7124-4 in unipolar single-channel weigh scale applications, but with design trade-offs. While both are 24-bit sigma-delta ADCs, the LMP90100MHX/NOPB has only one differential channel versus four in the AD7124-4, requiring a separate multiplexer if multiple load cells are used. Additionally, the AD7124-4 includes programmable current sources for RTD calibration, which the LMP90100MHX/NOPB lacks. If replacing, ensure the excitation voltage for the load cell is stable and within the LMP90100MHX/NOPB’s AVDD range, and use an external precision reference (e.g., REF5025) if better drift performance (≤3ppm/°C) is needed, as the internal reference may drift up to 10ppm/°C typical. Validate performance at cold start-up, as TI’s internal reference takes ~1ms to stabilize.

How does the LMP90100MHX/NOPB handle EMI susceptibility in industrial environments with variable frequency drives nearby?

The LMP90100MHX/NOPB integrates an input chopper-stabilized PGA to suppress 1/f noise and low-frequency drift, but its EMI susceptibility on analog inputs must be managed externally in noisy industrial settings. PCB layout plays a critical role: keep AIN traces short, shield high-impedance paths, and use π-filters (e.g., 10Ω series resistor + 10nF ceramic cap from AIN to AVSS) to attenuate RF ingress. Ground the sensor shield to the system star point, not locally, to prevent ground loops. Additionally, operate the LMP90100MHX/NOPB in unipolar mode with external reference if the environment introduces common-mode noise exceeding 100mVpp, as the internal PGA may saturate. Enable digital filtering (sinc 50/60Hz rejection) to mitigate line frequency interference from nearby VFDs.

What are the reliability risks when using the LMP90100MHX/NOPB in a high-humidity environment without conformal coating?

The LMP90100MHX/NOPB has a Moisture Sensitivity Level (MSL) of 3, meaning it can be exposed to floor humidity (≤60% RH) for up to 168 hours before solder reflow. Post-assembly, in high-humidity environments (>85% RH), leakage currents across the 4.40mm-width HTSSOP package can introduce offset drift or gain errors—especially on high-impedance input paths. Flux residues combined with condensation increase the risk of electrochemical migration. To mitigate, use no-clean or low-ionicity flux, implement conformal coating (e.g., acrylic or silicone), and include guard rings around AIN traces tied to AGND via 0Ω resistor for leakage control. Avoid exposing the device to rapid thermal cycling post-assembly to prevent moisture ingress through the mold compound.

How can output data rate (ODR) settings impact noise performance and line transient rejection when using the LMP90100MHX/NOPB in a 4-20mA loop-powered transmitter?

In 4-20mA loop-powered transmitters, the LMP90100MHX/NOPB must balance ODR and noise to maintain accuracy under line voltage fluctuations. At the maximum ODR (e.g., 2.5kSPS), the noise is higher (~12μVrms), reducing effective resolution—this impacts signal-to-noise ratio for small sensor signals like thermistors. Use lower ODRs (10–60SPS) with built-in sinc filters for better 50/60Hz rejection, especially if loop power supplies generate ripple. However, too low an ODR increases response time, risking instability in closed-loop systems. For optimal performance in loop-powered designs, set ODR to 50SPS, enable internal PGA gain (e.g., 128V/V), and power the VREFP from the loop supply via a low-dropout regulator (e.g., TPS7A16) to prevent AVDD dips during transients. Validate startup timing to ensure ADC synchronization with loop enable signals.

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