What are the critical layout considerations when designing a PCB for the LMH0387SL/NOPB to avoid signal integrity issues in high-speed amplifier applications?

When integrating the LMH0387SL/NOPB into a high-speed design, maintain tight impedance control on all SPI and amplifier output traces—typically 50Ω single-ended—using a solid ground plane directly beneath the 48-TLGA package. Minimize trace length between the device and load to reduce parasitic inductance, and ensure the thermal pad is properly soldered to a grounded copper pour with adequate via stitching for heat dissipation and grounding stability. Avoid routing high-speed signals near the edge of the board or across split planes to prevent EMI and crosstalk, which can degrade amplifier performance in sensitive analog paths.

Can the LMH0387SL/NOPB be safely replaced with the MC10EP89DG in an existing 3.3V SPI-controlled amplifier system, and what risks should I evaluate?

While the MC10EP89DG is listed as a substitute, direct replacement of the LMH0387SL/NOPB requires careful validation due to differences in interface logic levels, timing characteristics, and output drive strength. The MC10EP89DG operates at lower voltages (2.375V–3.465V) and uses ECL-compatible inputs, which may not be fully compatible with standard 3.3V CMOS SPI controllers without level shifting. Additionally, the output impedance and bandwidth profiles differ, potentially affecting amplifier gain flatness and stability. Always verify signal integrity, revalidate timing margins, and test under full load conditions before committing to a drop-in replacement.

How does the moisture sensitivity level (MSL 3) of the LMH0387SL/NOPB impact handling and assembly processes in a high-volume manufacturing environment?

The LMH0387SL/NOPB’s MSL 3 rating means it can be exposed to ambient conditions for up to 168 hours after opening the dry pack before requiring baking. In high-volume production, this demands strict inventory rotation (FIFO) and controlled storage (≤40% RH) to prevent moisture absorption that could cause popcorning during reflow. If the floor life is exceeded, bake the components at 125°C for 24 hours per JEDEC J-STD-033. Implementing automated moisture barrier bag sealing and real-time humidity monitoring at the SMT line reduces rework risk and ensures reliable solder joint formation on the 48-TLGA package.

What are the trade-offs of using the LMH0387SL/NOPB in a low-power portable amplifier design given its narrow 3.135V–3.465V supply range?

The LMH0387SL/NOPB’s tight supply voltage window limits battery selection and power management flexibility in portable systems. Alkaline or Li-ion batteries often drift outside this range during discharge, requiring a precision LDO or buck converter with ±1% output accuracy to maintain stable operation. While this ensures optimal noise performance and amplifier linearity, it adds cost, board area, and quiescent current. Consider whether the performance gain justifies the power architecture complexity—alternatives with wider supply ranges may simplify design if marginal SNR degradation is acceptable.

How should I handle ESD protection and grounding strategy for the LMH0387SL/NOPB in an industrial environment with high electromagnetic interference?

In electrically noisy industrial settings, protect the LMH0387SL/NOPB by placing TVS diodes on all SPI and amplifier I/O lines close to the connector, using low-capacitance devices (<5pF) to avoid distorting high-speed signals. Implement a star-ground topology with a single-point connection between analog and digital grounds near the device’s thermal pad to minimize ground loops. Shield sensitive traces with grounded guard rings and use ferrite beads on power inputs to suppress high-frequency noise. These measures prevent latch-up and ensure reliable SPI communication and amplifier fidelity under EMI stress.

Texas Instruments LMH0387SL/NOPB - Interface IC, 48-TLGA, SPI

Name: Texas Instruments LMH0387SL/NOPB
Brand: Texas Instruments
SKU: LMH0387SLNOPB
Price: 145.2900 USD
Availability: InStock
Rating: 5.0 (108 reviews)

Texas Instruments LMH0387 Product Overview

Texas Instruments LMH0387 is a highly integrated 3 Gbps HD/SD-SDI interface device built for equipment that must terminate directly at a BNC connector while preserving flexibility at the system level. Its most distinctive feature is the configurable BNC_IO pin, which allows a single physical BNC port to operate either as an SDI input with adaptive cable equalization or as an SDI output with cable-driving capability. This architecture is especially useful in broadcast, routing, monitoring, and field-deployable video systems where connector count, panel density, and board area are all constrained. Instead of assigning fixed receive and transmit ports early in the design, the hardware can remain more neutral and let product configuration, firmware policy, or SKU differentiation determine port behavior later.

At the signal-chain level, the LMH0387 addresses two very different physical-layer problems within one chip. In receive mode, it functions as an adaptive cable equalizer for SDI signals transported over coaxial cable. As cable length increases, the channel progressively attenuates high-frequency content, closes the eye, and increases timing uncertainty. The equalizer compensates for this frequency-dependent loss by dynamically shaping the incoming waveform to restore edge definition and amplitude characteristics before handing the signal to downstream logic. In transmit mode, the same device becomes a cable driver capable of launching SDI data onto the coaxial medium with the voltage swing and spectral behavior expected by the standard. This dual-use capability is not just a packaging convenience; it reduces the need for external switching networks and avoids some of the signal-integrity penalties that often appear when separate receive and transmit paths are multiplexed around the connector.

The supported rate range gives the device practical relevance across multiple generations of serial digital video. In receive mode, the LMH0387 handles 125 Mbps to 2.97 Gbps, which covers standard-definition, high-definition, and 3G-SDI operating points, as well as lower-rate variants used in adjacent transport schemes. In cable-driver mode, support extends from DC to 2.97 Gbps, which simplifies testing, pathological pattern handling, and low-frequency behavior at the line interface. Compliance with SMPTE ST 424, ST 292, ST 344, and ST 259 makes it suitable for mainstream SDI infrastructures, while DVB-ASI support at 270 Mbps broadens its utility in systems that straddle professional video and transport-stream environments. For mixed-format equipment, this matters because physical-layer components often become the hidden source of interoperability failures long before protocol logic does.

From an implementation perspective, the LMH0387 is best understood as an integration-oriented front end rather than a simple equalizer or driver. It combines adaptive equalization, cable driving, integrated return loss support, programmable signal conditioning, and SPI control inside a single 3.3 V device. That combination directly affects board design. A discrete approach typically requires separate receiver-side equalization, output-side cable drive, external control logic, and careful impedance management between stages. Each added transition increases sensitivity to parasitics, layout discontinuities, and power-supply noise. By collapsing these functions into one package, the LMH0387 shortens critical high-speed paths and reduces the number of analog interfaces that must be tuned on the PCB. In practice, fewer analog boundaries usually translate into faster bring-up and more repeatable compliance margins across manufacturing variation.

The configurable BNC_IO concept also changes how the surrounding system can be partitioned. In conventional SDI hardware, designers often commit each connector to a fixed direction because the analog front end is physically specialized. The LMH0387 relaxes that constraint. A matrix converter, portable recorder, smart monitor, or modular I/O card can expose a connector that is repurposed through software or boot-time configuration. This becomes valuable when the same hardware platform must support different operational modes, different customer profiles, or region-specific workflows. It also helps in serviceable products, where field configuration can recover utility from a limited number of panel connectors without redesigning the analog board. One subtle advantage here is inventory simplification: fewer hardware variants are needed when directionality becomes a configuration issue rather than a schematic-level commitment.

Adaptive equalization is central to receive performance, and it deserves more attention than a feature checklist usually gives it. SDI over coax is unforgiving because the data stream is uncompressed, high-rate, and timing-sensitive. Loss is not flat across frequency, so the channel distorts both amplitude and transition timing. The equalizer inside the LMH0387 must infer cable loss characteristics from the incoming signal and apply compensation without requiring manual tuning for each installation. This is important in real systems where cable type, connector wear, patch-panel routing, and environmental conditions vary. Designs that rely too heavily on nominal cable models often perform well on the bench but lose margin in deployed racks with aged coax or inconsistent interconnect quality. Devices with robust adaptive behavior tend to hold lock and maintain eye quality under more realistic operating conditions, and that usually matters more than peak reach under ideal lab cabling.

On the transmit side, cable-driver quality is not only about generating enough swing. Return loss, output matching, edge shape, and deterministic jitter all influence whether the downstream receiver sees a compliant signal after the cable and interconnect network have done their damage. The LMH0387 integrates return loss support and programmable signal conditioning, which gives designers a practical way to tune the launched waveform for the real channel instead of the textbook one. This is particularly useful when front-panel layout, connector footprint, ESD structures, and via transitions introduce small but meaningful discontinuities. In many SDI boards, the connector escape and protection network dominate the analog behavior more than expected. A device that provides some controlled adjustment at the line driver can recover margin that would otherwise be lost to physical implementation details.

SPI-based control adds another layer of system value. It allows software visibility and configuration over line-interface behavior, making the LMH0387 more adaptable than fixed-function analog parts. In products with embedded management, this enables mode switching, status monitoring, feature enablement, and factory calibration hooks without hardware changes. It also supports more disciplined board validation. During bring-up, engineers can explore operating conditions, compare cable-performance corners, and characterize output settings without cutting traces or swapping passive networks. This tends to compress debug cycles, especially when one board must support multiple SDI standards or dual-use connector roles. The broader lesson is that controllability in high-speed analog I/O is increasingly a system feature, not just a convenience for test.

Power and packaging choices are aligned with modern compact video equipment. Operation from a single 3.3 V supply simplifies integration into FPGA-, SoC-, and serializer-based designs where 3.3 V remains common for I/O-adjacent analog rails. The 48-pin 7 mm × 7 mm laminate TLGA package supports high-density surface-mount assembly while keeping interconnect lengths short enough for a 3 Gbps interface. Even so, package-level compactness does not remove the need for disciplined layout. Ground continuity, controlled-impedance routing, supply decoupling close to the device, and careful treatment of the BNC path remain critical. At these data rates, the board is part of the channel. A well-chosen equalizer/driver can compensate for cable loss, but it cannot fully rescue avoidable discontinuities introduced within a few centimeters of the connector or package breakout.

In application terms, the LMH0387 fits best where connector flexibility and integration density carry real product value. Broadcast cameras, production monitors, multiformat converters, router I/O cards, signal analyzers, and compact contribution encoders are strong examples. In these designs, every external connector has mechanical cost, front-panel cost, and routing cost. Allowing one BNC to operate as either source or sink can simplify the industrial design and increase functional density per panel area. It also makes sense in modular systems where the same hardware slot may need to behave differently depending on inserted firmware or role assignment. The part is less interesting in architectures with permanently fixed, high-count dedicated I/O where separate optimized receive and transmit paths are acceptable. Its real advantage emerges when flexibility itself is part of the product requirement.

A practical design pattern is to treat the LMH0387 as the boundary device between a relatively clean digital core and an unpredictable external coax environment. Upstream logic, whether FPGA-based processing or an SDI framer, benefits from seeing a conditioned, standard-compliant electrical interface rather than raw cable effects. Downstream, the outside world benefits from a driven signal that has been tuned for interoperability rather than merely generated. That separation of concerns usually improves design robustness. It also aligns with a broader engineering principle: high-speed interfaces become easier to scale when analog uncertainty is localized at the edge and made programmable.

There is also a strategic point in how this device should be evaluated. It should not be judged only by standalone equalization reach or output amplitude tables. Its real value lies in reducing analog fragmentation at the connector, enabling configurable port direction, and preserving signal integrity across multiple SDI formats with minimal external circuitry. In systems where time-to-market, reuse across product variants, and field-configurable I/O matter, that combination is often more important than squeezing out the last increment of isolated channel performance. The LMH0387 is therefore best viewed as a compact SDI port engine: one device that absorbs much of the electrical complexity of a BNC-facing video interface while giving the rest of the system more freedom.

Texas Instruments LMH0387 Positioning in HD/SD SDI System Design

Texas Instruments LMH0387 occupies a very specific but valuable position in HD/SD-SDI system design: it collapses two normally separate physical-layer roles, cable equalization on receive paths and cable driving on transmit paths, into one configurable device. In SDI equipment, this is more than a component-level convenience. It changes how ports are defined at the board level, how product variants are built, and how signal-routing architecture is planned around the FPGA or video processing core.

In a conventional SDI design, the receive side and transmit side are usually treated as distinct electrical domains. The input path needs adaptive equalization to recover a heavily attenuated coax signal and restore edge integrity after cable loss. The output path needs a driver with controlled amplitude, rise/fall behavior, and return-loss compliance to launch a standards-conformant signal into 75-ohm infrastructure. When these functions are implemented with separate devices, every BNC connector tends to become fixed early in the design as either an input or an output. That works in static products, but it limits reuse across platforms and creates friction when a product family needs multiple I/O configurations.

LMH0387 shifts that design assumption. By integrating both receive equalizer and transmit driver capability into a single programmable interface, it allows a port to be defined more by firmware or configuration intent than by hardwired board identity. This is especially useful in modular broadcast equipment, digital video servers, encoders, decoders, and distribution systems, where one hardware platform may need to support several market variants. A channel can be allocated as an SDI input in one design profile and as an output in another, without a major front-end redesign. That flexibility is often more important than the raw component count reduction, because it supports platform-based development instead of isolated board spins.

At the physical-layer level, the value of LMH0387 comes from where it sits in the signal chain. On the receive side, SDI equalization is not just amplification. The incoming signal from coax has frequency-dependent loss, so the higher-frequency content that defines timing transitions is attenuated more strongly than the low-frequency content. The equalizer must compensate for that channel loss profile while preserving jitter margin and maintaining reliable downstream clock/data recovery. If the equalization stage is poorly matched to the application, the recovered eye opening can remain marginal even when amplitude appears acceptable. Integrating the equalizer into a configurable dual-role device reduces the number of interface boundaries, which in practice helps control parasitics and simplifies channel validation.

On the transmit side, the driver must satisfy a different set of constraints. It needs to deliver the correct output swing into 75 ohms, maintain acceptable return loss across the relevant frequency range, and preserve edge characteristics without injecting unnecessary deterministic jitter. This is where integration matters in a second way. In many discrete implementations, external matching and return-loss tuning consume board area and often require iterative adjustment during bring-up. LMH0387 reduces that burden by incorporating return-loss network support and programmable interface behavior, which shortens the path from schematic to compliance-ready prototype. In systems with multiple SDI ports, that reduction in tuning effort scales quickly.

The strongest architectural advantage appears when the device is placed next to an FPGA-based video processing subsystem. Many modern SDI products concentrate format handling, framing, test-pattern logic, metadata insertion, and crosspoint behavior inside programmable logic. The external challenge is then to present the FPGA with a flexible but standards-compliant electrical front end. LMH0387 fits this model well because it decouples digital feature planning from fixed connector directionality. Instead of designing separate receive cards and transmit cards, or maintaining several BOM and layout derivatives, a single hardware platform can be structured around configurable SDI channels. This does not eliminate all port-planning constraints, but it significantly lowers the penalty for changing them.

That has practical consequences in product-line strategy. In broadcast and professional video systems, the differences between SKUs are often small from a signal-processing perspective but significant at the connector map. One model may require four inputs and four outputs. Another may require six outputs and two inputs. A third may reserve one connector for redundancy or loop-through behavior. If each variant depends on different equalizer and driver populations, inventory management becomes fragmented and validation effort multiplies. A configurable front-end device like LMH0387 helps consolidate these cases into a common PCB and a narrower procurement set. The savings are not only in component count. They also appear in reduced qualification paths, fewer sourcing dependencies, and more predictable manufacturing transitions when a design moves from prototype to volume.

There is also an important layout and signal-integrity angle. SDI interfaces are sensitive to impedance discontinuities, connector launch quality, and local return-path integrity. Every additional device transition increases the chance of creating reflections, peaking, or bandwidth limitations that are difficult to diagnose once the board is assembled. Combining equalizer and driver capability in one package does not solve poor layout, but it reduces the number of discrete high-speed analog interfaces that must be optimized independently. In dense chassis or modular cards where BNC routing competes with power planes, FPGA escape, and clock distribution, this simplification is often enough to improve first-pass success.

In practice, the main engineering benefit tends to show up during bring-up. Designs with separate receive and transmit devices often require more mode-specific probing and a wider matrix of fault isolation steps. When a port can switch roles, validation naturally becomes more systematic: connector path, configuration state, FPGA path, reclocking path if present, and output compliance can be tested as one reusable framework. That tends to expose board-level weaknesses earlier. For example, a channel that performs well as a transmitter but poorly as a receiver usually points toward input return-path issues, connector launch asymmetry, or power-supply noise coupling into the equalizer section. A more unified front-end makes these asymmetries easier to localize.

Another subtle advantage is in system resilience against requirement drift. SDI products rarely stay frozen after the first specification draft. Late requests for mirrored outputs, alternate monitor outputs, loop-through repurposing, or firmware-selectable connector roles are common in multi-function equipment. A rigid front end turns these requests into layout changes. A configurable device turns many of them into control and validation work instead. That distinction matters because firmware effort scales more gracefully than analog board rework, especially once the product has entered compliance testing or pre-production.

From a procurement standpoint, LMH0387 can simplify the bill of materials by reducing the need to stock separate equalizer and cable-driver devices for each port configuration. The more meaningful benefit, however, is BOM stability across a family of designs. Stable BOMs reduce forecasting noise and help avoid the hidden cost of supporting too many low-volume analog variants. In environments where lifecycle risk is watched closely, this kind of component consolidation can be as valuable as direct cost reduction.

The device is most compelling when the design objective is platform flexibility rather than absolute minimal analog specialization. If a product has permanently fixed, highly optimized SDI inputs and outputs with no need for role reassignment, discrete devices may still offer a narrowly tuned path. But in most equipment that balances feature density, variant reuse, and moderate to high channel count, integration at the SDI front end is usually the better systems decision. The gain is architectural cleanliness: fewer dedicated analog islands, fewer variant-specific constraints, and a cleaner mapping between physical connectors and programmable video functions.

Seen in that context, Texas Instruments LMH0387 is not simply a combo equalizer/driver. It is an enabler for configurable SDI port architecture. Its significance lies in allowing the physical interface to follow the product’s functional model instead of forcing the functional model to conform to a fixed analog partition. For HD/SD-SDI equipment built around reusable hardware platforms, that is often the difference between a board that supports one product and a board that supports an entire product family.

Texas Instruments LMH0387 Core Functional Architecture and Operating Modes

Texas Instruments LMH0387 is built around a bidirectional SDI interface concept in which one physical coaxial port can be repurposed as either a receive path or a transmit path. This is not just a convenience feature. It is a system-level architectural choice that reduces connector count, simplifies back-panel design, and enables flexible video I/O topologies in equipment that must support multiple operational profiles with limited board space.

At the center of the device is the BNC_IO node, which serves as the shared coaxial interface. Internally, the signal chain connected to this pin can be steered into one of two functional roles. In receive operation, the device behaves as an adaptive cable equalizer. In transmit operation, it becomes a cable driver with controlled output edge behavior. The TX_EN control pin determines which high-level path is active, making mode selection explicit and easy to integrate into hardware state control.

When TX_EN is low, the transmit driver connected to BNC_IO is disabled and the device operates as an input-side equalizer. Serial digital video arriving from the coax line is AC-coupled into the BNC_IO pin. At this point, the main challenge is compensating for frequency-dependent loss introduced by the transmission medium. Coaxial cable does not attenuate all spectral components equally. High-frequency content is attenuated more strongly than low-frequency content, which causes eye closure, transition softening, and reduced timing margin at the receiver. The LMH0387 addresses this with adaptive equalization, dynamically applying frequency compensation to restore the incoming waveform sufficiently for downstream processing.

This adaptive behavior is one of the device’s most important architectural traits. In SDI systems, cable length, cable type, connector quality, and installation condition can vary significantly. A fixed equalizer would only be optimal over a narrow operating range. An adaptive equalizer continuously interprets the incoming signal condition and adjusts its compensation profile so that the output remains usable across a wider span of link conditions. In practice, this improves design tolerance to field variability and reduces the need for manual tuning during production or deployment.

After equalization, the recovered signal is presented on the differential LVDS outputs, SDO and SDOB. These outputs are intended to interface cleanly with downstream deserializers, crosspoint switches, reclockers, or FPGA input stages. Differential signaling is used here for good reason. It improves common-mode noise rejection, supports high-speed data transfer with controlled swing, and fits naturally into modern digital video receive chains. In board-level layouts, keeping these differential traces short, impedance-controlled, and closely matched usually has a greater effect on margin than small differences in surrounding logic.

When TX_EN is high, the device switches into transmit operation. In this mode, differential serial input data is applied at SDI and SDIB, and the LMH0387 drives the BNC_IO pin as a coaxial cable output. The internal cable driver is designed to launch a signal suitable for SDI transport over a 75-ohm transmission environment. This function is more than simple level translation. The driver must deliver enough amplitude, maintain signal integrity through impedance discontinuities, and control edge shape so that the transmitted waveform remains compliant with applicable SDI requirements.

The selectable slew rate feature is especially relevant in this transmit role. Edge speed directly affects both compliance margin and practical electromagnetic behavior. If edges are too slow, deterministic jitter increases and the far-end eye can degrade. If edges are too fast, overshoot, ringing, and EMI become harder to control, especially on dense boards or in chassis with mixed-signal coupling paths. The LMH0387 allows slew optimization so the output can be tuned for different SDI standards and channel conditions. In real designs, this adjustment often becomes useful when moving from short internal test fixtures to full production cable assemblies, where connector launches and return-path quality begin to shape the waveform more visibly than expected from schematic review alone.

The mode-control scheme around TX_EN is straightforward, but correct usage matters because BNC_IO is a shared node. In receive mode, the output driver must remain disabled to avoid contention and to ensure the incoming coax signal is not disturbed. In transmit mode, enabling the driver places the cable interface under active drive, and the input-side receive path becomes nonessential unless the application explicitly requires local monitoring. Texas Instruments provides the option to place the receiver section into sleep mode through SPI while transmitting. This is a practical power-management feature, but it also helps reduce unnecessary internal activity in configurations where only one direction is valid at a time.

That SPI-controlled receiver sleep capability is more important than it may first appear. In modular video equipment, a port may spend long periods in a fixed direction depending on firmware configuration, routing state, or installed feature license. If the unused path remains active, power is wasted and thermal density rises for no functional benefit. In compact enclosures, even modest reductions in per-port dissipation can materially improve thermal stability, especially when many SDI channels are placed side by side. Designs that treat this as a first-order architectural parameter tend to achieve more predictable operating margins over temperature.

From a functional partitioning perspective, the LMH0387 can be viewed as three cooperating blocks: a receive equalization front end, a transmit cable driver back end, and a mode-control layer that arbitrates access to the shared coax connector. This partitioning is useful when integrating the part into a larger system because it maps directly to board-level concerns. The equalizer side is sensitive to signal integrity at the connector entry and AC-coupling implementation. The driver side is sensitive to output launch quality, return loss, and edge-rate selection. The control side is sensitive to power-state sequencing, firmware ownership, and protection against illegal port states.

In configurable port designs, this architecture is particularly effective. A single physical connector can support input mode in one product variant, output mode in another, or dynamic reassignment under software control. This reduces SKU fragmentation because the same hardware platform can be adapted to multiple use cases with minimal redesign. It also supports cleaner PCB reuse across families of equipment such as routers, monitors, converters, and test instruments. In systems where front-panel density is constrained, reclaiming even one connector position through bidirectional reuse can significantly improve feature packing efficiency.

There is also a less obvious system advantage. Using a device like LMH0387 encourages a cleaner separation between physical-layer capability and product behavior. The hardware no longer hardcodes the connector as strictly source-side or sink-side. Instead, behavior is defined by control policy. That opens the door to more adaptable firmware architectures, better manufacturing commonality, and easier field reconfiguration. The most robust implementations usually treat TX_EN and SPI power-state control as part of a supervised port-state machine rather than as isolated GPIO actions. This avoids transient ambiguity during startup, reset, or mode switching, where unintended drive enable timing can create difficult-to-debug link faults.

A practical implementation detail is that mode switching should not be treated as instantaneous at the system level even though the control interface is simple. The coax line, AC-coupling network, downstream receiver expectations, and upstream source activity all impose settling behavior. If the port changes direction under software control, the surrounding logic should sequence the transition so that the outgoing path is disabled before the incoming path is expected to lock, or vice versa. This prevents ambiguous link conditions and reduces false fault detection in supervisory software. Systems that ignore this often pass bench validation but show intermittent issues once cable hot-plug events and marginal sources are introduced.

Another point worth noting is that adaptive equalization solves cable loss, not every channel defect. Severe impedance mismatch, poor connector grounding, excessive stubs, or improperly chosen AC-coupling components can still degrade performance beyond what the equalizer can recover. Likewise, transmit slew adjustment can improve compliance margin, but it cannot compensate for a fundamentally poor output launch or badly controlled 75-ohm environment. The device is highly capable, but it performs best when the surrounding interconnect design respects transmission-line fundamentals.

Seen from this angle, the LMH0387 is not merely a receive equalizer combined with a transmit driver. It is a compact physical-layer building block for configurable SDI ports. Its value comes from how efficiently it merges adaptation, drive capability, and direction control around one coax interface. In systems that need flexible video routing with disciplined power use and minimal panel complexity, that combination is unusually effective.

Texas Instruments LMH0387 Standards Support, Data Rates, and Signal Reach

Texas Instruments LMH0387 is a multi-rate SDI cable equalizer and cable driver designed for broadcast video paths that must span several standards without changing the physical-layer architecture. Its standards coverage includes SMPTE ST 424 for 3G-SDI, ST 292 for HD-SDI, ST 344 for extended-rate serial digital transport, and ST 259 for SD-SDI. It also supports DVB-ASI at 270 Mbps. In practical system design, this standards set is not just a compliance checklist. It means one device can sit at the edge of routers, distribution amplifiers, camera interfaces, monitoring nodes, or patch-field recovery points and remain useful across mixed-generation infrastructure. That reduces BOM fragmentation and simplifies qualification, especially in facilities where SD, HD, and 3G links still coexist on the same coax plant.

The supported receive rate range of 125 Mbps to 2.97 Gbps is wide enough to cover most legacy and mainstream serial digital video links, while the integrated cable driver operates from DC to 2.97 Gbps. This asymmetry is important. On the receive side, the equalizer must recover attenuated, frequency-shaped signals that have traversed real coax with connector losses, return loss discontinuities, and installation-dependent aging. On the transmit side, the driver must launch a controlled SDI waveform with sufficient amplitude and edge fidelity to survive the next cable segment. Combining both functions in one part makes LMH0387 well suited for inline regenerative stages, loop-through outputs, or compact interface modules where board area and power budget are constrained.

From an engineering perspective, the real value of this device is not merely that it supports multiple data rates, but that it allows the same hardware platform to absorb uncertainty in field deployments. Video infrastructure is rarely homogeneous. A link may start as a short patch inside a frame, then later be repurposed for a long equipment-room run, or moved from SD service to HD or 3G service. A component that spans the full SDI rate stack avoids redesign at exactly the points where operational flexibility matters most.

Cable equalization reach is one of the defining parameters for LMH0387. On Belden 1694A coax, the equalizer can support up to 120 meters at 2.97 Gbps, 200 meters at 1.485 Gbps, and 400 meters at 270 Mbps. These numbers reflect the frequency-dependent attenuation of coaxial cable. As the bit rate rises, the spectral content shifts upward, and high-frequency loss becomes the dominant impairment. The equalizer compensates for that loss by applying inverse gain shaping, effectively reconstructing the amplitude relationship between low- and high-frequency components before the signal is handed to downstream logic or clock/data recovery stages.

Those reach figures should be read as system design anchors, not absolute guarantees under every installation condition. Belden 1694A is a known reference cable with predictable attenuation characteristics. Real links often include patch panels, BNC barrels, wall plates, and mixed cable lots, each introducing additional insertion loss and reflections. In bench evaluation, links that appear to pass comfortably at nominal length can lose margin quickly once connector density increases. A conservative design approach is to treat the published reach as a best-case baseline, then reserve headroom for routing complexity, temperature variation, and manufacturing spread. That headroom often determines whether a system remains stable after reconfiguration rather than only on the day it is commissioned.

The jitter specifications give a more useful view of signal integrity than reach alone. At 2.97 Gbps over Belden 1694A, equalizer output jitter is specified at 0.3 UI from 0 to 100 meters and 0.35 UI from 100 to 120 meters. At 1.485 Gbps, it is 0.25 UI from 0 to 170 meters and 0.3 UI from 170 to 200 meters. At 270 Mbps, it is 0.2 UI from 0 to 350 meters and remains 0.2 UI through 400 meters. These values matter because downstream CDR circuits, reclockers, FPGA receivers, and monitoring ASICs all consume timing margin. If the equalizer restores amplitude but leaves excessive deterministic or random jitter, the link may still fail despite nominal eye opening.

Unit interval based jitter numbers are especially useful because they normalize timing error to bit period. At 2.97 Gbps, one UI is much shorter than at 270 Mbps, so a similar absolute timing disturbance occupies a larger fraction of the bit cell. That is why high-rate SDI links are less forgiving of cable-induced distortion, poor launch quality, and discontinuities in the signal path. The slight rise from 0.3 UI to 0.35 UI near the maximum 3G reach is a reminder that equalization is operating closer to its compensation limit. In practice, that is the region where downstream tolerance, source quality, and PCB implementation begin to matter more than the equalizer data sheet alone might suggest.

A useful way to interpret these jitter figures is as part of a total link budget. The source contributes launch jitter and amplitude variation. The cable adds attenuation, return loss effects, and frequency-selective phase distortion. The equalizer removes much of the amplitude tilt but cannot erase every impairment, especially those caused by reflections or pathological source waveforms. The receiving CDR then has a finite tolerance window. Reliable design comes from allocating margin across all four blocks rather than expecting the equalizer to compensate for upstream weaknesses. In systems that fail intermittently, the root cause is often not insufficient nominal reach but an overconsumed jitter budget distributed invisibly across connectors, power integrity, and source edge quality.

The integrated cable driver extends the usefulness of LMH0387 beyond simple reception. After equalization, the recovered electrical signal can be re-driven onto another coax segment, allowing the device to serve as a compact restoration node. This is valuable in large routing frames, monitor walls, camera control areas, and mobile production systems where signal paths are frequently chained through intermediate equipment. Each regeneration point can effectively reset amplitude and edge conditions before the next cable section. That architecture is usually more robust than trying to stretch a single unregenerated coax run to its practical limit.

Board-level implementation strongly influences whether the device achieves its published performance. At SDI rates, the package pins and PCB traces are part of the channel. Short 75-ohm controlled-impedance routing, clean reference planes, disciplined return-current paths, and careful connector launch geometry all help preserve eye quality. Power supply filtering also matters. Equalizers and cable drivers operate on high-speed analog edges, so supply noise can modulate threshold crossings and degrade jitter. In dense broadcast cards, performance loss is often traced not to the SDI silicon itself but to small layout compromises around BNC transitions, via stubs, or insufficient local decoupling near the analog supply pins.

Another practical point is that maximum cable length and jitter performance should be validated with the actual source population, not only with ideal pattern generators. Some sources produce cleaner edges than others, and some pathological combinations of source pre-emphasis, cable aging, and connector wear can expose marginal behavior well before the nominal reach limit. Designs that include reclocking downstream may tolerate these conditions gracefully, while non-reclocked paths may reveal picture instability, CRC errors, or intermittent lock loss under temperature or routing changes. The stronger design choice is usually to validate near the boundary conditions where equalization transitions from comfortable compensation to aggressive recovery.

LMH0387 is therefore best understood as an enabler for broad-rate SDI physical-layer consolidation. Its standards support covers the dominant broadcast serial formats. Its receive and drive ranges allow one device to span multiple generations of video transport. Its cable equalization reach is strong enough for long coax runs in professional installations, and its jitter behavior remains controlled across those distances. The more important design insight is that its value grows when it is used as part of a disciplined signal-integrity strategy: realistic cable budgeting, conservative margin allocation, careful board implementation, and selective regeneration where the infrastructure demands it. Under that approach, the device is not just a standards-compliant interface component. It becomes a practical tool for building SDI links that remain stable across both nominal and imperfect real-world conditions.

Texas Instruments LMH0387 Input Mode Performance as an Adaptive Cable Equalizer

Texas Instruments LMH0387, when used in input mode, operates as an adaptive SDI cable equalizer rather than a simple line receiver. That distinction matters. Its job is not only to detect logic transitions, but to recover a heavily frequency-shaped serial stream arriving through coax with loss, dispersion, and amplitude reduction that vary strongly with cable length, cable type, connector quality, and data rate. In this mode, the device accepts the incoming SDI signal at BNC_IO, performs input equalization, and presents a differential LVDS output that is already terminated internally for 100 Ω operation. This simplifies the interface into downstream FPGA, reclocker, or SERDES logic and removes one common source of board-level mismatch errors.

At a system level, the LMH0387 should be viewed as a front-end conditioning stage. The incoming SDI waveform at the connector is rarely ideal, even when amplitude remains inside specification. Long coax runs suppress high-frequency content more than low-frequency content, so the eye arriving at the receiver is closed primarily by slope loss and intersymbol interference rather than by pure attenuation alone. The equalizer compensates this by applying frequency-dependent gain that restores transition sharpness and recovers usable eye opening. In practice, this means the receiver’s usefulness is tied less to absolute input amplitude and more to how effectively its adaptive equalization can reverse the channel loss profile for the actual installed cable plant.

The specified input swing in equalizer mode is 720 mVp-p minimum, 800 mVp-p typical, and 950 mVp-p maximum at 0-meter cable length. This parameter is easy to misread if taken in isolation. At zero cable length, the equalizer is effectively seeing a source with minimal channel loss, so the amplitude range mainly characterizes the direct front-end operating point. It does not imply that field performance should be judged only by connector-level swing at the source end. In deployed systems, return loss, pathological patching, and marginal launch amplitude can all degrade recoverability before nominal voltage limits are crossed. A design that passes lab checks with a short precision coax can still fail in the rack when presented with multiple connectors, aging cable, or slightly noncompliant transmitters. For this reason, it is usually more productive to validate the LMH0387 with stressed pathological patterns and realistic cable assemblies than with amplitude-only bench checks.

On the output side, the device provides equalized differential LVDS with 500 mVp-p minimum, 700 mVp-p typical, and 900 mVp-p maximum differential swing. The differential output level is specified at 250 mV minimum, 350 mV typical, and 450 mV maximum, with a typical output offset near 1.25 V. These values align well with direct digital interfacing requirements. Since the termination is internal, routing becomes more predictable and the receiver-to-FPGA connection can be treated as a short controlled differential interconnect rather than as a loosely defined high-speed analog node. That reduces component count, but it does not remove layout discipline. The equalizer may clean the cable-induced distortion, yet poor short-range board routing can still reintroduce skew, impedance discontinuities, or crosstalk at the handoff point. Keeping the LVDS pair tightly coupled, length-matched, and isolated from aggressive switching rails remains important, especially when the FPGA input margin is already being consumed by clock recovery tolerance or downstream jitter budgets.

Carrier detect is one of the more practical support features in the LMH0387. The CD output reports the presence state of activity on BNC_IO: high indicates no input signal, low indicates a detected signal. The CDTHRESH pin sets the detection threshold and can be left open or tied to ground for standard use. Although this looks like a small convenience feature, it often removes the need for separate analog supervision circuitry. In embedded receive chains, firmware can use CD as a fast hardware hint for cable insertion, source activation, or front-panel status updates. It also helps state machines avoid premature attempts at downstream lock acquisition when the input path is physically idle.

The deeper value of carrier detect appears during fault isolation. Loss of picture is not always caused by complete signal absence. It may come from insufficient launch level, poor equalization margin, damaged connectors, or a source that is active but not compliant enough for stable downstream processing. CD can distinguish “nothing present” from “something is arriving,” which is often enough to narrow the search space immediately. In practice, systems become easier to service when CD is sampled together with reclocker lock status, CRC error counters, and cable-length indication. That combination gives a rough but useful hierarchy: no carrier suggests physical disconnection or dead source; carrier with no lock suggests signal integrity or format issues; carrier with lock but rising error counts points toward margin collapse rather than hard failure.

The cable length indication feature extends that diagnostic model. It does not provide a precision time-domain estimate of physical cable distance. Instead, it exposes information derived from the equalizer’s internal adaptation state, which correlates with channel loss and therefore with effective cable length under expected cable conditions. Used correctly, this is operationally valuable. It can support maintenance interfaces, health monitoring, and automatic policy changes in equipment that must handle a wide range of installation scenarios. For example, a system can log an estimated cable condition during installation and later flag drift if the equalizer begins operating at a materially different setting for the same endpoint. That can reveal connector degradation, undocumented patch changes, or water ingress in legacy coax paths long before the link fails outright.

This feature is also useful when designing adaptive receive chains. If the estimated cable condition is consistently low-loss, power-sensitive equipment can remain in a conservative processing state and avoid unnecessary reach optimizations. If the indication trends toward longer or harsher channels, firmware can prioritize more robust downstream clock-data recovery settings, tighten alarm thresholds, or increase telemetry sampling around the receive path. The most effective use is not to treat cable length as an exact measurement, but as a proxy for equalization effort. That interpretation is usually more stable and more actionable.

Power behavior in equalizer mode reflects the same adaptive philosophy. Typical supply current is about 71 mA when equalizing cable lengths of 120 meters or less, and rises to roughly 91 mA to 113 mA for cable lengths above 120 meters. The device automatically shifts equalization stages at shorter cable lengths to reduce power. This is a strong indication that the internal architecture scales its analog effort according to inferred channel loss rather than running all equalization resources at full bias continuously. From an engineering standpoint, that is preferable to static worst-case biasing because it preserves reach where needed while reducing thermal load under common operating conditions.

That dynamic power profile has several practical implications. First, thermal characterization should include cable-dependent operating points, not just nominal room-temperature measurements with a short input lead. In dense video infrastructure cards, a receiver farm that sees mostly short patch links may dissipate very differently from one installed in a routing frame fed by long plant runs. Second, supply filtering must support current shifts without injecting noise back into sensitive analog nodes. Third, if system telemetry includes board current or local temperature, the receive path’s adaptive power changes can serve as an indirect indicator of channel stress. That signal is coarse, but in aggregate it can reveal deployment patterns that are not obvious from link status alone.

The Extended 3G Reach Mode, enabled through SPI, adds another dimension to this trade space. Forcing this mode can increase cable reach at 3G-SDI rates, but the datasheet notes that it reduces achievable cable lengths at HD and SD rates. This is not a minor footnote. It exposes a classic optimization boundary: extending equalization for one part of the operating envelope can compress margin elsewhere because the signal spectra and channel-loss interaction differ by SDI format. A design intended for a single known transport rate may benefit from fixing the mode for maximum reach. A multi-format product, however, should be cautious about hardwiring that choice unless the operational environment is tightly controlled.

In mixed-format equipment, the better strategy is usually policy-based control rather than static configuration. If the platform already identifies input format, the SPI setting can be selected to match actual use conditions. Even then, aggressive switching should be validated across edge cases such as source hot-plug, pathological test patterns, and marginal cable assemblies. Format changes are rarely isolated events; they often coincide with lock reacquisition, routing transitions, and power-supply transients elsewhere in the board. A mode change that looks safe in a quiet lab setup can expose race conditions when integrated into a larger signal chain. Stability during transitions matters as much as peak cable reach.

One useful way to think about the LMH0387 is as a margin translator between the analog coax domain and the digital processing domain. On the coax side, margin is consumed by attenuation, reflections, and spectral distortion. On the LVDS side, margin is consumed by timing uncertainty, threshold noise, and downstream recovery limits. The equalizer does not create margin from nothing; it reallocates recoverable signal content from the damaged channel into a form that digital logic can use. Because of that, overall receive robustness depends on balanced design across both sides of the interface. Overinvesting in equalizer capability while neglecting connector quality, return-loss control, or downstream clock recovery is rarely effective.

In actual product development, the strongest results usually come from treating the LMH0387 as part of a measured link budget rather than as a black-box fix for bad cabling. That means validating with representative cable types, varying launch amplitudes, realistic temperature ranges, and multiple SDI rates. It also means checking not only whether the receiver outputs toggling LVDS, but whether the complete chain maintains stable lock and error-free transport under stress. The device’s integrated termination, carrier detect, cable-condition visibility, and adaptive power behavior make that task easier, but they deliver the most value when their signals are exposed into firmware and diagnostics instead of left unused.

For engineers building robust SDI inputs, the LMH0387 stands out less because of any single electrical parameter and more because its behavior maps well onto real deployment problems. Its equalizer adapts to channel loss, its output interface is straightforward to integrate, and its support features expose enough internal state to improve observability. The key is to design around behavior, not just specifications: use carrier detect for state qualification, use cable-length indication as a channel-stress metric, evaluate power and thermal behavior across realistic cable conditions, and treat Extended 3G Reach Mode as a selective optimization rather than a default setting. That approach tends to produce receivers that are not only functional on the bench, but resilient in the field.

Texas Instruments LMH0387 Output Mode Performance as a Cable Driver

Texas Instruments LMH0387 in cable driver mode functions as a direct serial video line driver that bridges differential logic-domain data and a 75 Ω coaxial transmission environment through the BNC_IO output stage. In this mode, the device accepts differential serial data at SDI/SDI and translates it into a controlled single-ended output suitable for SDI transport over coax. This is not just a format conversion step. It is the point where logic timing quality, analog edge control, output amplitude accuracy, and cable-launch behavior converge into overall link robustness.

The output swing at BNC_IO is set by the reference resistor connected from RREF to VCC. With a nominal 715 Ω ±1% resistor, the specified output level is 720 mVp-p minimum, 800 mVp-p typical, and 880 mVp-p maximum. That range is aligned with SDI line requirements and reflects the fact that the LMH0387 is designed to operate as a standards-aware driver rather than as a generic high-speed buffer. In practical hardware, the RREF network deserves more attention than it often receives. Resistor tolerance, temperature coefficient, and local supply cleanliness all influence launch amplitude. A 1% part meets the stated condition, but in dense video platforms, placing this resistor close to the pin and away from fast return-current paths usually improves output consistency across boards and temperature.

The BNC_IO common-mode level is specified as 0.9 V + VCC - VEE, which indicates that the output stage operates around an internally defined bias point relative to the supply rails. For engineering use, this matters less as an abstract number and more as a constraint on interface compatibility and AC-coupling assumptions. In SDI transmission chains, the cable and receiver environment largely care about the launched differential-equivalent swing into the transmission system, but the local output bias still influences headroom, output transistor operating region, and large-signal transition symmetry. When supply margins are compressed or rail noise is elevated, common-mode behavior can subtly affect deterministic jitter and edge asymmetry before it becomes visible in a basic amplitude measurement.

The SDI input range is wide, from 100 mVp-p to 2200 mVp-p differential. That flexibility simplifies direct connection to FPGA serializers, reclockers, and video processing ASICs with different output standards and swing settings. A wide input sensitivity window is especially useful in systems where one PCB must support multiple upstream devices or where a prototype may evolve from LVDS-like swing levels to stronger current-mode logic outputs. The practical advantage is not only interoperability. It also reduces the need for external conditioning stages that would otherwise add latency, power, and jitter. Even so, the wide acceptance range should not encourage careless launch into the LMH0387 input. At multi-gigabit rates, clean differential routing, tight pair skew control, and disciplined return-current paths still determine whether the driver sees a valid eye with predictable crossing behavior.

One of the more valuable features in cable driver mode is selectable slew rate through the SD/HD pin. This is a highly practical design choice because SDI standards do not treat rise and fall time as a cosmetic parameter. Edge rate directly affects cable loss interaction, overshoot, return loss sensitivity, and jitter accumulation at the receiver. With SD/HD low, the device supports SMPTE 424M and 292M behavior for 3G and HD operation, with typical rise/fall times of 65 ps to 130 ps. These faster edges are necessary to preserve eye opening at higher data rates where transition density and channel attenuation quickly consume timing margin. With SD/HD high, the output is shaped for SMPTE 259M SD operation, and rise/fall time slows to 400 ps to 800 ps. That slower edge is not a compromise. It is usually the correct answer for 270 Mbps links because unnecessarily fast transitions at SD rates tend to increase ringing, EMI, and receiver stress without improving recoverability.

This slew-rate control is one of the cleaner examples of standards-aware analog design in mixed-signal video devices. A common integration mistake is to treat a serializer output as “good enough” if bit rate is correct. In reality, the line driver must match the transmission regime. A 3G-optimized edge launched into an SD path can produce waveform sharpness that looks attractive on a high-bandwidth scope while performing worse over real cable due to reflections and mask-margin erosion. Conversely, using SD-like edges at HD or 3G rates sacrifices transition fidelity and closes the eye at the receiver. The LMH0387 avoids the need for external analog reshaping by embedding this choice in the transmitter path, which simplifies the board and improves repeatability.

Output additive jitter is specified at 20 ps p-p for 2.97 Gbps, 18 ps p-p for 1.485 Gbps, and 15 ps p-p for 270 Mbps. These numbers are important because the cable driver sits late in the signal chain, where little downstream opportunity remains to repair timing degradation unless a reclocker is added. Additive jitter here directly consumes system budget. The scaling across bit rates is also instructive. As data rate rises, the same analog imperfections occupy a larger fraction of the unit interval, so the driver’s transition noise, output stage symmetry, and internal bandwidth become more consequential. In most video systems, these additive jitter figures are acceptable for direct transmission, but whether they are comfortable depends on the upstream source quality, cable length, connector discontinuities, and receiver equalization margin.

A useful way to interpret these jitter numbers is to separate random-looking contributions from layout-induced deterministic effects. The data sheet gives the device contribution under controlled conditions. Real assemblies add discontinuity-driven reflections, supply-coupled edge modulation, and pair-to-output conversion artifacts. For that reason, it is often unwise to allocate exactly the listed additive jitter into a system budget and assume compliance. A more resilient approach is to treat the transmitter as one term in a broader launch-quality envelope that includes supply ripple near the output stage, impedance control through the BNC transition, and any stubs created by test points or protection components. In many failed margin cases, the driver itself is not the limiting element. The loss of compliance comes from the way the driver is embedded into the board and connector structure.

Power behavior in output mode is equally relevant because cable drivers combine fast analog switching with moderate static bias currents. With TX_EN low and the equalizer in sleep mode, the typical supply current drops to 11 mA, which is useful for low-power standby states or designs that selectively enable outputs. In active output mode with the equalizer asleep, current is typically 57 mA for SD/HD = 0 and 50 mA for SD/HD = 1. The higher consumption in the faster-edge setting is expected because steeper transitions generally require greater dynamic current and wider analog bandwidth. In loopback mode, with both transmitter and receiver active and SD/HD = 0, current reaches 117 mA typical. That operating point matters for thermal density, especially in compact multi-channel designs where several devices may switch simultaneously.

For thermal planning, these current numbers should be converted into local power density rather than considered only as a rail-capacity issue. In practice, a single device current figure rarely looks threatening, but clustered SDI channels can create localized heating that shifts output amplitude, reference stability, and long-term margin. The transmitter often remains operational well before obvious thermal limits are reached, yet eye quality can soften as junction temperature rises. That is why solid ground stitching under the package, short supply decoupling loops, and low-impedance power distribution usually provide more benefit than simply checking average current against regulator capability. In multi-rate systems, the worst thermal case often occurs not in nominal SD operation but in mixed-function modes where loopback, fast-edge transmission, and active equalization coexist.

From an application standpoint, the LMH0387 is well suited for SDI transmit nodes that need a compact and standards-conscious cable launch stage. Typical use cases include broadcast interface cards, camera back-end modules, router outputs, monitor feeds, and FPGA-based video platforms that need direct coax drive without a separate discrete output network. Its broad input range simplifies coupling to digital sources, while selectable slew rate allows the same hardware platform to serve SD, HD, and 3G variants with minimal redesign. That reduces BOM fragmentation and makes field-configurable platforms more practical.

The most effective implementation strategy is to treat the device as an RF-aware video interface component rather than a generic digital peripheral. The differential input should be routed with controlled impedance and low skew. The output path from BNC_IO to the connector should be short, impedance-managed, and free from unnecessary shunt parasitics. The RREF resistor should be precise and physically close to the device. Supply decoupling should be staged, typically with a small high-frequency capacitor near the power pins backed by bulk capacitance nearby. If compliance margin is important, the board should be validated not only with eye diagrams at the output pin but also with cable-attached measurements across representative lengths, since the interaction between edge rate and channel loss is where the device’s analog behavior becomes fully visible.

A subtle but important strength of the LMH0387 is that it integrates decisions that are often mishandled when built from discrete logic and buffering elements. Output amplitude setting, standards-appropriate edge shaping, and controlled cable launch are all tied together inside one transmitter architecture. That usually yields better repeatability than assembling a path from a serializer, a generic high-speed buffer, and passive attenuation. The resulting design is not just simpler. It is generally easier to validate against SMPTE masks because the internal analog behavior was designed around the transport standard rather than around abstract bandwidth alone.

In that sense, the LMH0387 is best viewed as a signal-integrity component with a digital interface, not the other way around. Its specified swing, slew control, jitter performance, and current profile describe a transmitter optimized for preserving SDI compliance from logic boundary to coaxial medium. When implemented with careful attention to reference accuracy, output launch geometry, and power integrity, it provides a stable and efficient cable driver stage that can carry a wide range of serial video formats with predictable margin.

Texas Instruments LMH0387 SPI Control, Programmability, and System-Level Flexibility

Texas Instruments LMH0387 extends beyond a fixed-function SDI equalizer by exposing a practical SPI control plane that makes the device easier to tune, adapt, and integrate at system level. That matters because equalizer performance is rarely determined by silicon capability alone. It is shaped by cable loss profile, source launch conditions, board parasitics, downstream interface requirements, and power-state strategy. The SPI interface turns the LMH0387 from a static signal-path component into a configurable element that can be aligned with those conditions instead of forcing the rest of the design to absorb the mismatch.

At the pin level, the SPI interface uses MOSI, MISO, SCK, SS, and SPI_EN. SPI_EN is a mode-gating signal and should be held high in input mode. In output mode, it may also be held high when SPI access is desired. This detail is easy to overlook, but it directly affects bring-up behavior. If SPI_EN is left floating or handled inconsistently across operating modes, register access can become ambiguous during initialization and fault recovery. The internal biasing helps, but it should not be treated as a substitute for deliberate control. SS includes an internal pullup, while SPI_EN includes an internal pulldown. These defaults are useful for preventing undefined states during power sequencing, yet robust designs still drive both pins explicitly from the controller or with clear strap logic. That approach reduces startup variation and avoids hidden dependencies on ramp rate or reset timing.

The main value of SPI support is programmability of analog operating points that are otherwise fixed in simpler equalizers. The LMH0387 allows adjustment of receiver output common-mode voltage and output swing, launch amplitude optimization for the equalizer path, sleep-mode entry for power reduction, and additional function control through its register map. These controls are not cosmetic. They are the interface between signal integrity theory and field behavior. Output common-mode and swing settings determine how cleanly the LMH0387 hands off data to the next stage, especially when that stage has limited common-mode tolerance or tight input sensitivity. In mixed-vendor receive chains, this kind of adjustment often removes the need for unnecessary AC-coupling changes, resistive attenuation patches, or excessive downstream equalization.

Programmable launch amplitude optimization is especially important because real SDI links are not uniform. A textbook channel assumes a known transmitter amplitude, predictable cable attenuation, and stable connector behavior. Actual deployments do not behave that way. Different upstream devices can launch at different amplitudes, and even compliant transmitters can occupy different parts of the acceptable range. Cable assemblies also introduce variation through length, construction, aging, and connector quality. In that environment, a fixed equalizer setting may work functionally while still leaving margin on the table. The LMH0387 addresses this by allowing fine tuning through SPI. The datasheet identifies nominal equalizer tuning by writing 30h to register 02h. That value is a sound baseline, not a universal optimum. In practice, it is best treated as the center of a controlled search space.

A useful engineering pattern is to start from the nominal setting, validate operation across the expected cable matrix, then step the launch optimization register while observing pathological cases rather than ideal ones. The best setting is often not the one that produces the cleanest eye on a short reference cable. It is usually the one that preserves lock stability and jitter tolerance at the edge of the supported channel set while avoiding overcompensation on easier links. This distinction matters in production designs. A configuration tuned only for best-case lab conditions can create intermittent failures when the system is exposed to weak launchers, long runs, or marginal patch panels. The SPI-adjustable equalizer lets the design target robust operation instead of peak-looking scope plots.

Output common-mode and swing programmability also deserve more attention than they usually receive. In high-speed serial signal chains, interface failures are often blamed on equalization first, even when the real issue is receiver-to-receiver electrical mismatch between stages. If the LMH0387 drives an FPGA input bank, reclocker, cable driver, or crosspoint, the downstream device may have preferred input amplitude and common-mode windows that are not perfectly aligned with default settings. Being able to trim those parameters can improve eye opening at the next receiver without changing topology. This is one of the quieter advantages of the LMH0387: it gives the designer a way to shape the interface boundary electrically, not just recover the incoming signal.

Sleep-mode control is another feature that becomes more valuable at system scale than it appears on a feature list. In dense video equipment, thermal headroom is often consumed by many always-on high-speed paths, not by one dominant device. If the LMH0387 is embedded in a router, monitor, test instrument, or modular I/O card, SPI-controlled sleep allows unused channels to be parked without requiring board-level power switching. That simplifies sequencing and can reduce thermal interaction between adjacent channels. It also improves deterministic recovery because the control processor can manage state transitions explicitly rather than relying on coarse external gating.

From a digital integration perspective, the SPI timing is uncomplicated. The interface supports SCK up to 20 MHz, with 4 ns setup and hold requirements for MOSI and SS-related timing, and 15 ns timing for MISO delay and tri-state transitions. These values are well within the capability of typical MCUs and FPGAs, so the control path is rarely implementation-limited. The more relevant design question is not whether the host can toggle the bus fast enough, but how register writes are coordinated with mode changes, signal presence, and fault handling. In FPGA-managed systems, it is often effective to treat the LMH0387 register file as part of the channel state machine rather than as a one-time boot configuration. That enables structured responses such as applying known-good profiles per input class, reloading settings after watchdog events, or shifting to low-power mode when carrier detect is absent.

In board-level implementation, several details improve reliability with little cost. Keep SPI routing disciplined but not overengineered; at 20 MHz, clean reference return and sensible edge control matter more than exotic layout techniques. Avoid sharing the SPI bus with noisy, high-current peripherals unless chip-select isolation and firmware arbitration are well defined. Drive SPI_EN deterministically, especially if the device can operate in both input and output roles across product variants. During bring-up, read back critical registers rather than assuming writes succeeded. That simple step catches polarity mistakes, pin strap conflicts, and bus contention early. It also shortens debug cycles when a configuration issue masquerades as an analog signal problem.

One deeper point is that programmability in devices like the LMH0387 should be used to reduce analog uncertainty, not to compensate for weak channel design. SPI tuning can widen margin, align interfaces, and support operational flexibility. It should not be the first remedy for avoidable layout loss, poor connector selection, or uncontrolled impedance discontinuities. The strongest use of the SPI feature set is therefore selective and measured: establish a sound physical channel first, then use the programmable controls to normalize variation that cannot be designed out. When applied this way, the LMH0387 becomes more than an equalizer with registers. It becomes a controllable signal-integrity node that supports repeatable deployment across a wider range of sources, cable plants, and system architectures.

Texas Instruments LMH0387 Pin-Level Design Considerations and External Component Requirements

The LMH0387 integrates cable equalization, reclocking support functions, and a configurable coax interface into a compact signal path, but its external network still determines whether the device behaves like a robust SDI front end or merely a functional lab prototype. The part removes much of the traditional discrete return-loss and port-sharing circuitry, yet several pins remain highly sensitive to component value, placement, grounding, and parasitic coupling. In practice, the device should be treated less like a generic digital IC and more like a mixed-signal transmission-line element with embedded analog control loops.

At the center of the interface is BNC_IO, the shared analog input/output node connected to the coax connector through an AC-coupling capacitor, typically 4.7 μF. This pin is the physical expression of the device’s configurable-port architecture: the same external connector can support receive, transmit, or adaptive behavior depending on system mode. That flexibility is valuable, but it also concentrates multiple performance constraints onto one PCB region. The capacitor value is not arbitrary. It must be large enough to avoid excessive low-frequency droop and pattern-dependent baseline movement across the supported SDI rates, while also presenting low enough impedance across the operational spectrum so that the coax path remains transparent. In production layouts, the dielectric and package style of this capacitor matter more than is often assumed. A nominal 4.7 μF part with poor high-frequency behavior or excessive ESR/ESL can degrade edge fidelity and worsen return loss at the connector interface. Compact placement between the BNC launch and the device pin is therefore not just a routing preference; it is part of the analog channel design.

The board region around BNC_IO deserves the same discipline normally reserved for RF connectors. The trace from the BNC center pin to the coupling capacitor and onward to the device should be short, impedance-controlled, and free of unnecessary stubs or via transitions. Ground continuity around the connector shell and launch area should be dense and symmetric so that the signal return path does not spread unpredictably into adjacent copper. A recurring issue in dense layouts is the temptation to place mode-control traces, status lines, or power neck-downs close to BNC_IO because the pin appears digitally managed at the system level. Electrically, it is not. Coupling from nearby fast edges can reduce margin long before eye-diagram degradation becomes obvious in basic bring-up tests. Designs that pass initial link checks but fail under long cable conditions often reveal this kind of local interference near the shared coax node.

The equalizer control loop depends on the capacitor connected between AEC+ and AEC-, specified as 1 μF. This capacitor is part of the adaptive equalization loop filter, so it directly influences the loop’s dynamic behavior. The function is not merely decoupling. It shapes how the internal equalizer responds to cable attenuation, process spread, and signal variation. If the capacitor is substituted with a value that is electrically similar only at low frequency but significantly different in effective capacitance at bias and temperature, equalizer convergence behavior can shift. The result may appear as inconsistent lock acquisition, varying jitter tolerance, or reduced robustness with marginal cable assemblies. Placing this capacitor close to the pins and keeping the loop compact reduces pickup into what is effectively an analog control node. One useful design habit is to isolate this area from aggressive digital return currents, especially from nearby clock or FPGA banks, because noise injected into the loop filter can modulate equalizer behavior in subtle ways that are difficult to debug from software-visible status alone.

The unused receiver input termination at TERMRX should be implemented as a 1 μF capacitor followed by a 220 Ω resistor to ground. The unused transmitter output termination at TERMTX should be implemented as a 4.7 μF capacitor followed by a 75 Ω resistor to ground. These networks are easy to misclassify as optional housekeeping components, but they are better understood as analog boundary conditions for internal signal paths. When a receiver or transmitter path is not actively used, the corresponding termination network prevents the internal port structure from floating into undefined impedance states. This matters because the LMH0387 internally multiplexes and shares signal resources around the coax interface. Leaving these pins improperly terminated can create reflections, control instability, or unexpected coupling into the active path. In early hardware spins, these terminations are sometimes omitted to save space under the assumption that unused means irrelevant. That assumption usually fails once full mode coverage, cable stress, or EMI testing begins.

The difference between the TERMRX and TERMTX networks also reflects the different electrical roles of the receive and transmit sides. The 220 Ω condition on the receiver-related node is not trying to emulate a live cable load directly; it is establishing the internal environment expected by the unused path. The 75 Ω condition on the transmitter-related node more closely relates to coax-system loading conventions. The AC-coupling capacitors in both cases isolate DC biasing while preserving the intended AC termination behavior. Placement should still be local to the respective pins. Long routes between the pin and its termination convert a simple resistive boundary into a distributed structure with avoidable parasitics.

The RREF pin is one of the most production-critical support pins because it sets the BNC_IO output driver level through a nominal 715 Ω resistor to VCC. This resistor effectively calibrates the output amplitude, so tolerance, temperature coefficient, and supply quality all influence transmitted signal compliance. It is common to think of this as a static set resistor, but it is better viewed as a precision analog reference element. A wide-tolerance resistor or noisy local supply can move output swing enough to consume compliance margin, especially when combined with connector loss, board attenuation, and process variation. Using a precision resistor with controlled drift is usually worth the negligible cost increase. Locating it close to the pin and tying it to a clean VCC region helps keep the reference stable. If output amplitude variation appears across builds, the first review point should not only be resistor tolerance on paper, but also resistor technology, supply routing, and local contamination from adjacent switching currents.

Reserved pins marked RSVD must remain unconnected. This requirement should be interpreted literally. They should not be tied to ground, tied to supply, used as mechanical anchors, connected through test pads, or absorbed into copper pours. Reserved pins in mixed-signal devices often connect to undocumented internal structures used for characterization, trim, future revisions, or test modes. Any external connection can alter internal bias conditions or expose latent behaviors that are invisible during basic bench validation but emerge across lot variation or temperature extremes. A clean implementation leaves pad escape and surrounding copper arranged so that accidental plane contact cannot occur during layout optimization or later board revisions. It is also wise to lock these pads in design-rule reviews because automated stitching or copper-pour refill operations can unintentionally violate the do-not-connect condition.

Although the LMH0387 integrates the return-loss network internally, return-loss performance still depends materially on board design. This is a key point because high integration can create false confidence. Internal integration reduces component count and narrows the variability associated with discrete matching networks, but it does not eliminate the physics of the connector launch, PCB dielectric, pad geometry, via fields, and return-current continuity. The datasheet’s note that the device exceeds return-loss specifications on the evaluation board should be read as a statement about the quality of the complete channel implementation, not just the silicon. Reproducing that margin requires attention to the launch from the BNC into the controlled-impedance trace, minimization of discontinuities at the coupling capacitor pads, and a low-inductance ground structure around the interface.

Connector launch geometry is often the dominant hidden variable. A theoretically correct 75 Ω trace cannot compensate for a poor transition from the BNC footprint into the board stackup. Excess pad length, anti-pad imbalance, sparse ground stitching, or abrupt width changes can create localized impedance steps large enough to affect return loss and eye quality, especially at higher data rates. In compact systems, routing constraints sometimes force the coax path through layer changes or around nearby structures. Each such compromise should be treated as a measurable signal-integrity event. If a via transition is unavoidable, it should be designed with controlled return path continuity and, where possible, with surrounding ground vias to confine the field. The integrated return-loss circuitry inside the device performs best when the external channel presented to BNC_IO is already well behaved.

A useful way to approach the LMH0387 layout is to separate pins into three classes. First are signal-interface pins such as BNC_IO, where transmission-line behavior dominates. Second are analog-control pins such as AEC+, AEC-, and RREF, where local noise and component stability determine loop accuracy and output calibration. Third are structural-support pins such as TERMRX, TERMTX, and RSVD, where the correct boundary condition is more important than apparent activity. This classification helps avoid a common failure mode in mixed-signal board design: treating all low-pin-count support nets as equally noncritical. They are not. The highest-risk pins are often the ones carrying little obvious logic activity.

From an application standpoint, these details become more important as cable length, environmental variation, and interoperability demands increase. A short in-rack connection may appear tolerant of mediocre launch design or loose reference resistor selection, while long-reach SDI paths expose every margin deficit at once. Systems intended for field deployment should therefore validate not only nominal link operation, but also behavior across cable grades, connector wear conditions, supply corners, and temperature spread. In many cases, the layout that looks merely “clean enough” in CAD becomes the limiting factor once real coax assemblies and compliance measurements enter the loop.

The strongest designs usually come from treating the LMH0387 not as a black-box SDI transceiver, but as a carefully partitioned analog front end with digital configurability layered on top. When the external capacitors define stable analog conditions, the precision resistor preserves output amplitude, the reserved pins remain truly isolated, and the BNC launch is engineered as part of the channel, the device’s internal integration works as intended. That is where the practical benefit of the part appears: fewer external networks to tune, but only if the remaining ones are implemented with full awareness of their electrical role.

Texas Instruments LMH0387 Electrical, Thermal, and Environmental Characteristics

Texas Instruments’ LMH0387 is defined around a narrow and intentional operating envelope. It runs from a single 3.3 V rail, with a recommended supply range of 3.14 V to 3.46 V. That specification is more than a nominal power note. It reflects the voltage headroom required by the device’s internal analog and mixed-signal circuitry to maintain timing integrity, amplitude control, and equalization behavior across process and temperature variation. In practical board design, this means the 3.3 V rail should not be treated as a loosely regulated utility supply. It should be a low-noise, well-decoupled rail with controlled transient behavior, especially in systems where the LMH0387 shares power infrastructure with FPGAs, serializers, or switching regulators that inject broadband noise and dynamic load steps.

The free-air operating temperature range of -40°C to 85°C places the device solidly in the industrial category. For video infrastructure, broadcast equipment, and transport-layer hardware deployed in racks, mobile platforms, or field-installed enclosures, this is a meaningful range. It indicates that the device is intended to preserve functional performance under cold-start conditions, elevated ambient temperatures, and long-duration thermal soak. In practice, however, ambient temperature alone rarely determines real operating stress. The more relevant variable is local board temperature near the package, which is driven by airflow shadowing, adjacent power components, and copper density beneath the device. In compact SDI processing cards, it is common for the local thermal environment to exceed the chassis ambient by a wide margin, so the published operating range should be read together with thermal resistance and power dissipation, not in isolation.

The absolute maximum ratings define the device’s survival boundaries, not its usable region. The supply voltage limit of -0.3 V to 4 V, input voltage range of -0.3 V to VCC + 0.3 V, maximum junction temperature of 125°C, and storage temperature range of -65°C to 150°C are stress thresholds intended for reliability analysis, fault containment, and protection design. A recurring design mistake is to treat these values as temporary operating allowances. That approach compresses reliability margin and can accelerate latent degradation, particularly in fine-pitch mixed-signal devices where oxide stress, input clamp conduction, and localized self-heating are not immediately visible at the functional level. A more robust interpretation is to view absolute maximum ratings as “do not cross” boundaries and to create normal operating conditions with measurable distance from them under worst-case line, load, and thermal scenarios.

Input voltage compliance deserves particular attention in systems with hot-pluggable interfaces or poorly sequenced rails. Because the valid input range only extends slightly beyond the supply rails, any external signal that arrives before VCC is established can forward-bias protection structures. The result may not be immediate failure, but repeated events of this type often manifest later as increased leakage, parameter drift, or intermittent startup behavior. In multi-board video systems, this is especially relevant when one module can back-drive another through connectors during staggered power-up. Small series resistors, controlled interface sequencing, and careful clamp design usually prevent this class of issue with minimal signal penalty.

The LMH0387’s ESD ratings provide a useful view of handling robustness. The device is specified for ±6000 V under the human-body model, ±2500 V under the charged-device model, and ±300 V under the machine model. These numbers indicate respectable resilience for standard assembly and service environments, but they should not be interpreted as immunity in uncontrolled handling or cable-level surge conditions. The distinction matters. Component-level ESD ratings measure survivability under standardized test waveforms at the package pins. Real equipment often experiences different stress profiles, particularly at external connectors where discharge current can couple into shield structures, return paths, or nearby high-speed traces. In other words, strong component-level ESD capability is beneficial, but board-level robustness still depends heavily on layout discipline, grounding strategy, and the placement of external protection elements where applicable.

In manufacturing flow, the charged-device model rating is often the more operationally relevant number than the human-body model figure, because automated handling, tray transfer, and pick-and-place processes can generate rapid discharge events directly from the component body. For that reason, standard ESD controls remain necessary even when the published values appear comfortable. Ionization, grounded tooling, moisture control, and disciplined packaging practices continue to matter. Experience with high-density video boards shows that ESD-related fallout often does not appear as catastrophic failure at test. Instead, it may present as marginal equalization range, unstable lock behavior, or channel-to-channel variation that consumes debug time long after assembly. Preventing that class of latent damage is far more efficient than screening for it later.

Thermal behavior is defined by the package-level resistances of the 48-pin TLGA. The junction-to-ambient thermal resistance is 64.5°C/W, the junction-to-case top thermal resistance is 20.8°C/W, and the junction-to-board thermal resistance is 32.3°C/W. These values describe different heat-flow paths and should be used according to the system’s dominant cooling mechanism. Junction-to-ambient is useful for first-order estimation in still air under standardized board conditions, but it is often the least representative figure in a finished product. Junction-to-board is usually more informative when the PCB serves as the primary heat spreader, which is common in dense video platforms. Junction-to-case top becomes relevant when airflow or mechanical thermal coupling above the package contributes meaningfully to cooling.

A simple thermal estimate illustrates the point. If the device dissipates 300 mW, using the junction-to-ambient figure alone predicts a junction rise of roughly 19°C above ambient. At 70°C local ambient, that places the junction near 89°C, which appears acceptable. But if the board is densely populated and neighboring devices elevate the effective local thermal environment, the real junction temperature can climb notably higher. This is why thermal design for parts like the LMH0387 should be based on board context, not only datasheet arithmetic. Copper area under and around the package, via stitching into internal planes, airflow direction, and proximity to hotter components all change the result in ways that matter at industrial temperature limits.

Mode-dependent supply current also deserves explicit consideration. In video-path devices, power dissipation is rarely constant across all operating states. Data rate, cable loading, signal activity, and internal processing modes can shift current consumption enough to alter thermal margin. Designs that pass thermal validation in a nominal lab configuration sometimes lose margin in field conditions when all channels are active, when input cable equalization is working harder, or when the enclosure fan curve has been reduced for acoustic reasons. A disciplined approach is to evaluate worst-case power in the highest throughput mode, at the upper end of supply tolerance, and with the least favorable airflow condition. That tends to reveal the true thermal boundary early.

From a reliability planning perspective, the most useful way to read these electrical, thermal, and environmental characteristics is as a coupled system. Supply integrity affects power dissipation. Power dissipation affects junction temperature. Junction temperature affects long-term parameter stability and lifetime. Mechanical layout influences both thermal behavior and ESD current paths. Good designs treat these variables together rather than as separate checklist items. For the LMH0387, that usually means a tightly regulated 3.3 V rail, local high-frequency decoupling close to the supply pins, clean return paths, controlled input stress during sequencing, and a PCB layout that allows the package to shed heat efficiently into the board.

In professional video hardware, the parts that create the fewest problems over time are usually not the ones with the widest absolute limits, but the ones integrated into a design with deliberate margin. The LMH0387 supports that approach well. Its industrial temperature capability, defined ESD performance, and characterized thermal package data make it predictable. Predictability is often the decisive advantage in infrastructure equipment, because it allows the design team to move from electrical compliance to manufacturability and then to long-term field stability without relying on hidden margin or optimistic assumptions.

Texas Instruments LMH0387 Typical Application Value for Video Infrastructure Equipment

Texas Instruments LMH0387 is positioned as a highly practical interface device for SDI-centric video infrastructure, especially in equipment built around SMPTE ST 424, ST 292, and ST 259 transport layers. Its value is not just that it supports these standards, but that it compresses two normally separate edge functions—cable equalization on the receive side and cable driving on the transmit side—into a single device. In video systems where front-end signal integrity often dictates overall platform reliability, that level of integration directly improves board utilization, I/O flexibility, and lifecycle maintainability.

At the signal-chain level, the LMH0387 sits at the boundary between the coaxial SDI domain and the differential logic domain used by FPGAs, video processors, and timing devices. In equalizer mode, it compensates for frequency-dependent loss introduced by long coax runs. This matters because SDI eye degradation is rarely caused by a single impairment; it is usually the accumulated result of cable attenuation, connector discontinuities, return loss, and marginal source amplitude. A robust equalizer restores usable signal margin before the data reaches downstream clock and data recovery stages. In cable driver mode, the same device performs the inverse edge function, taking differential electrical input from digital logic and producing a standards-compliant SDI output suitable for outbound coax transmission. This duality makes the device especially effective in platforms where ingress and egress port allocation may change across product variants.

In modular video equipment, this creates a meaningful architectural advantage. A single PCB can expose a BNC interface and defer the role of that connector until late in the product definition cycle. The port can operate as an SDI input or SDI output depending on assembly option, control configuration, or firmware policy around the surrounding logic. That reduces the need for separate receive-card and transmit-card layouts, which in practice lowers validation overhead and simplifies inventory control. The deeper benefit is that this approach decouples mechanical design from product segmentation. Once enclosure cutouts, panel labeling strategy, and high-speed routing constraints are solved on a common platform, multiple product roles can be derived with much less disruption than a traditional dedicated-port design would require.

This kind of SKU flexibility becomes more valuable as product families expand. In compact routers, gateway units, or modular frames, it is common to discover late in integration that market demand does not align with the original port mix. A design built around a fixed receive-only or transmit-only SDI front end usually forces either a board respin or a compromised derivative. With the LMH0387, the edge interface remains adaptable, so the surrounding FPGA image and system software can carry more of the role differentiation. That is often a better engineering trade because digital feature changes scale more cleanly than analog front-end redesign.

The device also maps well to FPGA-centric video architectures. On the receive side, LVDS outputs provide a natural electrical interface into FPGA I/O banks or dedicated deserialization paths. On the transmit side, differential inputs align with the signaling style already present in digital video processing pipelines. This reduces the amount of interface translation required at the board edge and helps preserve timing cleanliness. In practice, every extra translation stage near a high-speed video port tends to introduce cost, power, routing complexity, and another opportunity for jitter or common-mode sensitivity. A part that fits the native electrical environment of the logic fabric usually pays off well beyond its footprint.

For distribution amplifiers and routing subsystems, the LMH0387 addresses both ends of the coax path in a way that suits real installation conditions. Long inbound cable runs are common in broadcast plants, event production systems, and multiroom facility wiring, where the actual installed path may differ significantly from the nominal design assumptions. Equalization margin therefore becomes a system-level risk reducer, not just a component feature. On the outbound side, standards-compliant cable driving is equally important. In SDI systems, marginal launch amplitude or poor edge shape may still appear functional on a short bench cable while failing across longer field runs or through patch infrastructure. A device intended specifically for compliant SDI transmission avoids that trap and gives more predictable interoperability across mixed-vendor installations.

Maintenance and diagnostics are another area where the LMH0387 has practical value. Carrier detect can be used as a low-level health signal for system management logic, allowing the control plane to distinguish between upstream signal absence, cable disconnect, and deeper processing faults. Cable length indication adds another layer of observability. It does not replace full physical-layer instrumentation, but it is often enough to identify whether a link is operating near the edge of equalization capability or whether an installation issue is likely tied to unexpected cable conditions. When integrated into alarms, logs, or remote management telemetry, these signals reduce troubleshooting time substantially. In field support workflows, simple status points like these are often more useful than complex metrics that are difficult to interpret under time pressure.

A well-executed design can use those monitoring functions more intelligently than basic fault reporting. For example, system software can correlate carrier detect transitions with crosspoint switching events, power sequencing, or FPGA reconfiguration states to isolate whether a failure is external or local. Cable length indication can also inform adaptive operational policy, such as flagging ports that should not be assigned to higher-risk paths or identifying installation zones where passive infrastructure quality is degrading. The broader point is that physical-layer awareness should not remain trapped at the connector; in resilient video equipment, it should feed upward into supervisory logic.

There is also a subtle but important design strategy enabled by the LMH0387: standardizing the SDI edge across an entire platform. When a product line uses the same equalizer/driver device in multiple nodes—input cards, output cards, compact converters, and distribution modules—signal behavior becomes more predictable across the family. That simplifies compliance characterization, eases SI validation, and reduces the number of analog corner cases that have to be rediscovered in each new design. In high-speed video hardware, consistency is often underestimated. A repeatable front-end architecture usually contributes more to shipping stability than adding isolated feature complexity in each module.

From an implementation perspective, the part is most effective when treated as part of a complete channel design rather than as a drop-in connector companion. Power integrity, reference plane continuity, BNC launch geometry, differential pair symmetry, and return-current control all influence how much real margin the equalizer or driver can preserve. In bench bring-up, many SDI issues that first appear to be protocol or FPGA problems end up tracing back to connector footprint optimization, local supply noise, or avoidable routing imbalance near the device. The LMH0387 provides the right functional primitives, but extracting full value still depends on disciplined RF-aware layout and realistic cable-condition testing.

Its strongest application fit is therefore in systems that need both technical compliance and product configurability: digital video servers, modular processing frames, encoders, decoders, routing subsystems, and distribution amplifiers. In those environments, the LMH0387 is not merely a physical-layer component. It is an architectural lever that allows one hardware platform to cover multiple SDI roles while preserving interoperability, observability, and signal integrity at the point where video systems are usually most exposed to real-world failure modes.

Potential Equivalent/Replacement Models for Texas Instruments LMH0387

Potential replacement evaluation for the Texas Instruments LMH0387 requires more than a part-number cross check. The device is not just an SDI equalizer or just a cable driver. It collapses several signal-chain functions into one programmable interface element, and that integration defines both its value and its replacement difficulty. Any upgrade path, second-source strategy, or redesign effort should therefore start from the architectural role of the device, not from its headline data rate alone.

The LMH0387 sits at the boundary between the coaxial medium and the internal digital video path. On the receive side, it performs adaptive cable equalization over a wide operating range. On the transmit side, it drives SDI signals back onto the cable. The more unusual aspect is that it supports a shared BNC-connected node that can be configured as either input or output. That means the part is not simply processing SDI; it is also simplifying connector topology, reducing front-end component count, and shaping the board-level impedance environment through its integrated return loss network and programmable output behavior. Once these functions are bundled into a single device, replacement analysis becomes a system problem rather than a component problem.

From the documentation provided, no direct equivalent or vendor-identified alternate part is named by Texas Instruments. That absence is significant. In practice, when a vendor does not point to a migration path within the same document set, it usually means the product occupies a narrow functional niche or that compatible substitution depends heavily on implementation details outside the silicon itself. For this reason, the correct question is not “What part has similar bandwidth?” but “What device or device set can reproduce the same electrical behavior, interface model, and mechanical constraints with acceptable redesign cost?”

The first screening layer is core function matching. A candidate must replicate the LMH0387’s combined single-chip role as an SDI equalizer and cable driver. If a proposed alternative only equalizes incoming SDI but cannot drive the line, or can drive the line but lacks adaptive equalization, then it is not a true replacement. It may still be a workable redesign option, but it changes the system partitioning. That distinction matters because a two-chip receive/transmit front end introduces new routing constraints, power-supply noise coupling paths, control sequencing issues, and potentially a different failure signature under cable stress or marginal signal conditions.

The second layer is interface topology. The shared BNC I/O model is one of the strongest barriers to substitution. Many available SDI front-end parts assume distinct receive and transmit ports. The LMH0387’s architecture enables a more compact external connector arrangement and can reduce switching complexity at the board edge. Replacing it with separate input and output devices may require additional analog switching, relay logic, or connector reallocation. Each of those changes affects return loss, insertion loss, isolation, and electrostatic robustness. In high-speed coaxial systems, those board-edge changes often dominate real-world performance more than the silicon datasheet would suggest.

The third layer is standards coverage and rate span. A replacement should support ST 424, ST 292, ST 344, ST 259, and DVB-ASI at 270 Mbps, while covering receive operation from 125 Mbps to 2.97 Gbps and transmit operation from DC to 2.97 Gbps. This range is broader than many nominal “3G-SDI capable” components actually support in practice. Some devices meet the upper rate requirement but are optimized for a narrower set of SDI operating conditions. Others support the right standards but have limitations at the low end, especially where pathological patterns, long cable losses, or legacy transport modes are involved. A candidate that passes a simple bitrate check can still fail interoperability in mixed-format equipment.

Equalization reach is another non-negotiable parameter. The LMH0387 is specified for up to 120 m at 2.97 Gbps, 200 m at 1.485 Gbps, and 400 m at 270 Mbps on Belden 1694A. These numbers are not just marketing values. They encode assumptions about the equalizer’s gain adaptation range, peaking behavior, jitter tolerance, and loss compensation strategy relative to a known cable model. Substituting a device with weaker reach, or with a reach rating based on a different cable family, can alter the operational envelope in subtle ways. A system may still pass bench tests with short patch cables but fail in field installations where longer runs, aged coax, or non-ideal terminations expose the difference.

SPI programmability should also be treated as a primary requirement rather than a convenience feature. The LMH0387 allows programmable control over equalizer behavior and output characteristics, which means the host system can tune operation for mode selection, output edge shaping, and likely service diagnostics. If a replacement uses pin-strapping instead of SPI, or offers a reduced register model, firmware and hardware assumptions may both break. The impact is usually larger than expected. Monitoring software, manufacturing test scripts, and in-system calibration behavior are often built around the control model of the original part. A substitute that is electrically acceptable but operationally opaque can increase validation time more than a moderate schematic redesign would.

Selectable slew rate deserves similar attention. At SDI rates, edge control is tightly linked to eye opening, EMI behavior, and return loss performance through practical cabling and connector structures. Faster is not always better. In many designs, a programmable slew setting is the hidden mechanism that allows a product to pass across multiple cable lengths and connector wear conditions without overdriving the interface. Devices lacking comparable control may create a sharper eye on the bench while producing worse interoperability in deployed systems. That tradeoff appears frequently when replacing integrated cable drivers with generic high-speed outputs.

Power and package constraints form the next filtering layer. The LMH0387 operates from a single 3.3 V supply and comes in a 48-pin TLGA package. If footprint compatibility matters, then many otherwise acceptable devices are excluded immediately. Even when the replacement is electrically superior, changes in package type, thermal path, escape routing, and supply decoupling geometry can force a board respin. With high-speed coax interfaces, that respin often extends beyond the device footprint into the surrounding impedance-controlled network. In other words, package mismatch is rarely a localized issue.

A practical evaluation matrix should separate drop-in replacement from functional replacement. A drop-in replacement must align across pinout, package, power rails, control interface, and analog behavior at the connector boundary. Functional replacement only needs to preserve system-level capability, even if it requires new circuitry or firmware changes. These two categories are often conflated in procurement discussions, but they lead to very different risk profiles. For the LMH0387, a true drop-in option appears unlikely based on the available documentation. Functional replacement is more realistic, but it may require a two-chip architecture and a revised coax front-end network.

When assessing possible substitutes, the most effective sequence is usually this: first confirm receive equalization range and transmit amplitude behavior against the target cable set; then validate connector-side return loss with the actual board stackup and BNC implementation; then verify standards interoperability across all intended rates; and only after that evaluate software control alignment and lifecycle factors. This order tends to expose real incompatibilities earlier. It avoids a common mistake where teams overemphasize nominal standard support and under-test analog boundary behavior. In SDI hardware, the mismatch usually appears first at the connector, not in the digital core.

Board-level return loss implications deserve explicit emphasis. The LMH0387 includes an integrated return loss network, which means part of the impedance management strategy is embedded in the device itself. A substitute without an equivalent internal network shifts that responsibility onto external passives and layout. That change can be manageable, but it removes a degree of predictability. Small layout differences around the launch, AC-coupling structure, or protection network can then become first-order variables. This is one reason replacements that look straightforward on a block diagram often become unstable in validation. The original device may be compensating for board-edge imperfections in ways that are easy to overlook.

In redesign scenarios, a split implementation using one adaptive equalizer and one SDI cable driver can be viable if the shared-port requirement is relaxed or reimplemented externally. However, this should be treated as a controlled architectural migration, not a substitution. Once the signal path is split, the design inherits inter-device matching concerns, additional power domains or filtering requirements, and more complex fault handling. It also changes the maintenance model. Field failures become harder to localize because degradation can occur in either receive conditioning, transmit drive, or the switching network between them. Integrated parts reduce that ambiguity, and that operational simplicity is often undervalued during component sourcing.

Another useful perspective is to treat the LMH0387 as a connector-facing subsystem in a single package. That framing helps explain why straightforward equivalents are rare. The part absorbs analog compensation, line driving, switching flexibility, and control programmability into one edge-interface device. Replacements should therefore be evaluated as subsystem replicas. If an alternative cannot reproduce the same cable-facing behavior with similar control granularity, then it is not truly equivalent even if the internal SDI data path remains intact.

For procurement and sustaining engineering teams, the practical implication is clear. Screening should cover not only data rate and standards support, but also shared-port architecture, SPI control compatibility, supply strategy, package impact, output edge programmability, and especially return loss behavior at the board level. A candidate that satisfies only the protocol layer is not enough. The closer the original design depends on the LMH0387’s integrated analog behavior, the less likely a drop-in replacement becomes.

The most defensible path is to define replacement requirements in three tiers. Tier one covers mandatory electrical behavior: receive range, transmit range, cable reach, and standards support. Tier two covers architectural fit: shared BNC use model, return loss handling, slew control, and programmability. Tier three covers implementation fit: 3.3 V operation, package constraints, firmware effort, and validation burden. Any candidate that fails tier two should be classified as a redesign option, not a substitute. That classification prevents false equivalence early and keeps sourcing decisions aligned with actual engineering risk.

Texas Instruments LMH0387 Selection Considerations and Design Trade-Offs

Texas Instruments LMH0387 is most compelling in platforms where the BNC port cannot be treated as permanently fixed. Its value is not simply that it combines receive and transmit functions, but that it allows a single hardware footprint to support multiple product roles with minimal board changes. In systems that may ship as an input module, an output module, or a field-reconfigurable node, that flexibility can remove an entire board spin. If the interface direction is known and immutable from the start, a dedicated cable equalizer or cable driver often remains the cleaner choice because signal flow is simpler, control logic is lighter, and verification scope is smaller. The LMH0387 becomes attractive when platform reuse, SKU reduction, front-panel density, or connector consolidation matter more than absolute simplicity.

The central design trade-off starts with the shared BNC_IO architecture. That shared node is what enables configurability, but it also collapses the margin for control errors. TX_EN is not just a convenience pin; it defines whether the device is actively driving the line or presenting the path needed for reception. In practice, this means control sequencing must be treated as part of the signal-integrity design, not just firmware housekeeping. If TX_EN changes at the wrong time, or if the inactive path is not terminated as intended, the result is not merely functional ambiguity. It can become return-loss degradation, unstable signal amplitude, receiver sensitivity loss, or visible compliance failure at the connector. This is one of those areas where integration saves area but shifts discipline into mode control and board-level validation.

A useful way to think about the LMH0387 is as a configurable coax interface endpoint rather than a simple serializer-side accessory. Once viewed that way, the importance of state management becomes clearer. Direction control, standby behavior, cable presence assumptions, and power state transitions all interact at the physical layer. Designs that treat these as independent software states often end up discovering edge cases late in validation. Designs that define a strict interface state machine early tend to avoid most of those issues. A small amount of upfront rigor here usually saves disproportionate debug time around intermittent link behavior.

The integrated return-loss network is another strong integration feature, but it should not be mistaken for immunity to poor layout. It reduces external component count and lowers the risk of implementing the matching network incorrectly at schematic level. However, return loss in an SDI path is still heavily shaped by launch geometry, via structure, reference continuity, and connector implementation. The package, escape routing, and transition into the BNC footprint still define whether the internal advantages are preserved. Short routing alone is not sufficient. The current path must remain controlled, especially across layer transitions and near reference splits. In dense boards, this often becomes the limiting factor before the silicon does. The practical lesson is straightforward: when the datasheet says the network is integrated, read that as fewer analog parts to tune, not as permission to relax RF-grade layout discipline.

This becomes even more important because the LMH0387 is often selected specifically to save space. Space-efficient designs naturally push components closer, increase routing congestion, and make impedance control harder near the panel connector. The part can enable a smaller architecture, but the board must still provide a physically clean coax launch. In many compact layouts, moving one nearby aggressor, reducing one via stub, or improving one return path does more for SDI robustness than changing several passive values elsewhere. With integrated interface devices, layout quality often dominates the final result more than the feature list suggests.

Extended 3G Reach Mode introduces a different kind of trade-off. It is tempting to view it as a free cable-length extender, but it is better understood as an operating-point shift optimized for a specific regime. Improving 3G performance usually means the receive path is being biased toward conditions that are less optimal for HD and SD behavior. The datasheet warning that HD and SD cable length capability may be reduced is therefore not a side note; it is a direct statement that reach optimization is format-dependent. In mixed-format products, this matters more than peak 3G reach. A system that occasionally handles SD, HD, and 3G in the same field deployment may be better served by predictable balanced behavior than by maximum reach in one mode.

The practical implication is that mode selection should follow the real deployment profile rather than a headline specification. If the application is fixed at 3G and cable quality is highly variable, Extended 3G Reach Mode may provide meaningful system margin. If the product is format-agnostic, enabling it by default can quietly narrow interoperability. This is one of the more common traps in configurable video interfaces: optimizing for the worst-case lab cable in one format can reduce resilience across the actual installed base. The strongest designs usually choose conservative default behavior and expose more aggressive tuning only when the use case truly supports it.

Power behavior deserves similar scrutiny. The LMH0387 supports low-power states, but its supply demand is not static and should not be budgeted as a single nominal number. Current draw moves with operating mode, cable loading, signal activity, and whether both receive and transmit sections are enabled. In a single-channel design this may be easy to absorb. In a multi-channel router, monitor wall, or modular video platform, it compounds quickly. Regulator sizing, plane width, local decoupling, and thermal spreading all need to reflect the worst realistic concurrency, not just a per-channel typical value multiplied by channel count.

This point is often underestimated because interface devices appear digitally managed and therefore seem power-predictable. In reality, analog front-end activity changes with line conditions. Long cable runs, marginal equalization conditions, and active output drive all influence dissipation. In dense systems, thermal clustering near the rear-panel interface can become the practical ceiling. A design may meet electrical requirements on paper and still exhibit elevated local temperature that narrows long-term margin. Good power planning for LMH0387-based boards therefore means characterizing current in each meaningful operating state and validating temperature with multiple channels stressed simultaneously. That work is especially worthwhile when channels can switch dynamically between idle, receive, and transmit roles.

The packaging choice adds a manufacturing dimension that should be evaluated as early as the electrical fit. The 48-pin TLGA package can be attractive for compact layouts and high-density front-end integration, but it changes assembly assumptions compared with leaded packages. Inspection strategy, rework limits, stencil design, paste volume control, and board warpage tolerance become more important. X-ray capability may move from optional to routine depending on manufacturing flow and quality targets. For organizations used to leaded analog packages, this is not necessarily a blocker, but it does shift risk from schematic complexity toward process control. The best sourcing decision is usually the one that aligns package capability with the existing assembly ecosystem, not just the one that minimizes board area.

This is also where procurement and engineering need to stay tightly coupled. A package that is electrically ideal but operationally awkward can increase hidden cost through yield loss, inspection burden, or supplier constraints. In low- to medium-volume builds, that overhead can outweigh the benefit of a slightly smaller footprint. In high-volume products with mature process control, the same package may be entirely appropriate. Manufacturability fit is therefore not a secondary concern. For interface devices like the LMH0387, it is part of system architecture because the package directly influences how confidently the analog performance can be reproduced in production.

From a platform strategy perspective, the LMH0387 is strongest when the product roadmap values optionality. It allows one PCB to support different connector roles, different market SKUs, and in some cases field-configurable behavior, all without duplicating the SDI interface section. That can simplify inventory, shorten derivative development, and reduce front-panel redesign effort. But the integration gain is only real if the team is prepared to manage the additional control, validation, and layout precision that come with a shared I/O architecture. Integration in this class of device does not eliminate complexity; it relocates complexity into state control, physical implementation, and corner-case verification.

For that reason, the selection decision should be framed around where complexity is easiest to manage in the target organization. If board area and product reuse are the dominant constraints, the LMH0387 is often a strong fit. If the product has a fixed direction, limited firmware infrastructure, and little tolerance for interface-state edge cases, discrete dedicated parts may still produce a more robust development path. The most successful LMH0387 implementations usually come from teams that intentionally exploit its flexibility rather than merely tolerate it. When the device is used as a deliberate platform enabler, its integration advantages are significant. When used only to collapse a schematic, its trade-offs become more visible.

Conclusion

Texas Instruments LMH0387 is best understood as an SDI front-end integration device for professional video equipment that must receive and transmit serial digital video over coax while keeping the external interface compact, robust, and standards-aligned. Its main advantage is not only that it combines an adaptive cable equalizer and a cable driver in one device, but that it does so in a way that directly addresses the most failure-prone part of many SDI designs: the BNC-facing physical layer. In practical board-level architecture, this reduces the number of discrete interface stages, shortens the signal path between receive and transmit functions, and gives the designer tighter control over signal integrity, channel recovery behavior, and output edge characteristics.

At the mechanism level, the receive side is built to compensate for frequency-dependent loss introduced by coaxial cable. As cable length increases, high-frequency components of the SDI stream are attenuated more strongly than low-frequency content, which causes eye closure, timing uncertainty, and eventually loss of lock. The LMH0387 addresses this with adaptive cable equalization, automatically reshaping the incoming signal so that the downstream processing chain sees a restored data stream with improved amplitude and transition definition. This matters because SDI links are especially sensitive to cumulative degradation across connectors, patch fields, and aging cabling. In real installations, the nominal cable reach listed in a datasheet is rarely the whole story; connector quality, return loss discontinuities, and routing practices often determine whether a link is stable or only marginally operational. A device with well-behaved adaptive equalization therefore provides more than distance extension. It increases tolerance to imperfect field conditions.

Its support for SD-SDI, HD-SDI, and 3G-SDI operation up to 2.97 Gbps makes it suitable for equipment that spans legacy and newer professional video formats. This multi-rate capability is especially valuable in platforms that are reused across product variants or deployed in mixed-format facilities. A common issue in such systems is that interface hardware tends to be over-specialized early in development, which later complicates product line scaling. A component like the LMH0387 avoids that trap by giving a single hardware interface path enough flexibility to cover multiple SDI operating modes. That reduces redesign pressure when the same mainboard must support several feature tiers, I/O module options, or regional deployment profiles.

The integrated return loss network is another feature with disproportionate system value. Return loss is often treated as a compliance detail, but in practice it is tightly linked to overall interface stability. Poor impedance matching at the coax interface produces reflections, and reflections degrade both receive robustness and transmit waveform quality. By integrating the return loss network, the device reduces dependence on large numbers of precision external matching components and lowers the risk of implementation drift between schematic intent and actual production behavior. This also shortens tuning cycles during validation. In BNC-based layouts, where connector launch geometry, via structure, and ground continuity all influence performance, reducing the number of external analog dependencies usually improves repeatability from prototype to volume build.

The programmable receiver behavior adds useful control at the system integration level. In many video products, not every SDI input path operates under identical conditions. Some ports are front-panel user-facing connections exposed to variable cable quality. Others are internal or semi-controlled links with known channel characteristics. Programmable receive-side settings let the designer optimize behavior for lock sensitivity, recovery margins, and fault handling rather than forcing every port into one generic configuration. This is particularly relevant in modular equipment and router-adjacent systems, where link conditions can vary widely over time. Fine-grained control is often the difference between a design that merely passes compliance in the lab and one that behaves predictably in service racks, mobile units, or long patch-chain environments.

On the transmit side, selectable slew rate is a practical and often underappreciated feature. Faster edges can help preserve timing margins, but they also increase spectral content, raise EMI risk, and make layout discontinuities more visible in the output waveform. Slower controlled transitions can improve overall emission behavior and reduce overshoot or ringing on shorter or cleaner links. The ability to choose transmitter slew characteristics gives the board designer a way to align output behavior with the actual mechanical and electrical environment of the product. In dense systems with multiple SDI outputs, this can materially simplify EMC tuning. It also creates room for a more intentional tradeoff between standards margin and emission control rather than treating output edge rate as a fixed property.

From a port architecture perspective, the LMH0387 is most valuable where receive and transmit functions are both needed near the coax boundary and board area is constrained. Video servers, codec platforms, modular broadcast frames, monitoring equipment, and distribution amplifiers fit this pattern well. In these systems, space pressure is not just about PCB area. It also affects thermal concentration, connector placement, keep-out regions, and the routing complexity around high-speed traces. Combining equalization and driving into one configurable component helps simplify floorplanning. It can also reduce inter-device routing between discrete receiver and transmitter stages, which improves controllability of impedance and limits opportunities for signal degradation.

This integration has a procurement and lifecycle dimension as well. A combined-function SDI interface device can reduce total component count, simplify inventory, and streamline assembly in the right design context. However, that same integration increases replacement sensitivity. Substitution cannot be done by checking data rate alone. The equalization profile, output amplitude behavior, return loss implementation, control interface compatibility, power rail requirements, and layout assumptions all matter. In practice, second-source evaluation for combined analog front-end devices usually requires partial redesign or at least a fresh validation cycle. For this reason, the LMH0387 should be selected not merely as a part number that meets an SDI checkbox, but as a platform decision tied to product longevity, sourcing strategy, and maintenance expectations.

A useful design pattern is to place this device at the physical I/O boundary and treat it as the signal-conditioning anchor for the SDI path. That means the surrounding circuitry should be chosen to preserve the advantages it provides. Power supply noise must be controlled carefully, especially near the cable driver. Ground stitching around the BNC launch should be tight and symmetrical. Trace lengths between connector and device should be minimized and impedance-managed. If relays, ESD devices, or protection structures are inserted into the path, their parasitic effects must be evaluated against return loss and eye performance rather than assumed harmless. Experience with SDI hardware repeatedly shows that the interface IC may be fully standards-capable, yet the assembled port still underperforms because of connector launch geometry, poorly chosen protection parts, or fragmented ground return paths.

In application scenarios such as encoders and decoders, the LMH0387 supports cleaner partitioning between the video processing core and the external transport layer. The processing FPGA or ASIC can remain focused on stream handling, format processing, and clock-domain management, while the LMH0387 manages the analog realities of coax transmission and reception. In distribution amplifiers and looping equipment, its integrated nature supports denser channel counts without forcing excessive analog component sprawl. In modular systems, it can enable a common SDI interface block that is replicated across cards with minimal variation, which helps both design reuse and manufacturing consistency.

The deeper value of the LMH0387 is that it addresses an engineering truth common in professional video hardware: SDI reliability is usually won or lost at the interface boundary, not in the digital payload path. A design that simplifies that boundary while preserving configurability is often more valuable than one that offers isolated best-in-class receive or transmit specifications but requires a more fragile implementation. In that sense, the LMH0387 is a strong choice for flexible BNC-based SDI designs because it aligns electrical performance, integration efficiency, and implementation practicality in one device. For teams selecting parts for long-lived professional video products, that balance is often more important than any single headline specification.