LMH0387SLE/NOPB

LMH0387 product overview and positioning in SDI interface design

The LMH0387 occupies a very specific but highly useful position in SDI interface design: it is not just a signal-path component, but a port-definition device. Its real value is not merely that it integrates a cable equalizer and a cable driver in one package. The more important point is that it allows a single coaxial connector, typically a BNC, to be assigned as either an SDI input or an SDI output without changing the core hardware architecture. That capability directly affects platform design, inventory strategy, board routing, and field configurability.

At the electrical level, SDI systems usually separate receive and transmit functions into different devices because the analog requirements at each side of the coax link are distinct. On the receive side, long coaxial cables introduce frequency-dependent attenuation, amplitude loss, and edge degradation. Recovering a compliant SDI waveform requires adaptive equalization that compensates for cable loss across a wide operating range. On the transmit side, the challenge shifts to generating a properly conditioned serial stream with sufficient output swing, return loss performance, and signal integrity to drive 75 ohm coax while maintaining SMPTE mask compliance. The LMH0387 combines both roles, which is a meaningful integration because these two functions often define the analog boundary of an SDI channel.

This integration changes the design model. In a conventional architecture, an input BNC is permanently tied to an equalizer and an output BNC is permanently tied to a driver. That approach is straightforward, but it fixes signal direction at layout time. The LMH0387 enables a different strategy: build a generic coax interface node and configure its role according to product SKU, firmware mode, card personality, or system deployment requirements. For modular video systems, this is especially valuable because the same board can be repurposed across multiple applications with fewer component changes and less layout divergence. In practice, that tends to reduce both schematic fragmentation and qualification effort, which often matter more than the raw component count.

The device is aligned with the key SDI standards that define mainstream professional video transport. Support for ST 259 covers SD-SDI rates, ST 292 covers HD-SDI, ST 424 addresses 3G-SDI, and ST 344 extends transport support for lower-rate data mappings. DVB-ASI support at 270 Mbps further broadens its utility in mixed video and broadcast transport environments. This standards coverage is important because many deployed systems do not operate at a single fixed data rate. Routers, encoders, monitoring gear, patch interfaces, and modular processing frames often need to tolerate signal-rate variation across generations of infrastructure. A component that spans SD, HD, and 3G rates reduces edge-case design work and lowers the risk of building narrow-function hardware into a broad-function platform.

The receive path deserves attention because adaptive equalization is often treated as a checkbox feature when it is actually one of the main determinants of field robustness. In SDI over coax, the loss profile of the cable is shaped by both length and frequency. As bitrate increases, the higher-frequency content of the serial signal is attenuated more heavily, and the eye opening at the receiver collapses. An adaptive equalizer restores this by selectively compensating for the loss profile, allowing reliable recovery of the serial stream after substantial cable attenuation. What matters in system terms is not just maximum cable reach on a datasheet, but stability across varying cable types, connector quality, patch-panel insertion loss, and marginal installations. Devices in this class are often judged in the lab by nominal cable-length performance, but they tend to prove their value in installations where several small degradations stack together. A robust equalization path absorbs that variability.

The transmit side is equally important in high-density designs. A cable driver for SDI must do more than launch bits onto coax. It must maintain waveform fidelity under impedance discontinuities, connector parasitics, and layout imperfections while meeting the output characteristics expected by downstream equipment. In practical board design, transmit compliance is heavily influenced by placement around the BNC launch, return-current continuity, power-supply cleanliness, and the quality of the 75 ohm environment. The LMH0387 simplifies the transmit chain by integrating the driver function with the configurable I/O concept, but that does not eliminate the need for disciplined RF-style layout. In fact, the more flexible the port architecture becomes, the more important it is to preserve a controlled analog perimeter around each connector.

This is where the LMH0387 becomes strategically useful in modular and scalable products. In systems such as video servers, encoder or decoder platforms, and distribution amplifiers, the front-end connector map is often shaped by product segmentation as much as by raw technical need. One product variant may need four inputs and two outputs, while another may need the reverse. Without a configurable device, these variants often force different PCB versions or underused circuitry. With the LMH0387, a common board can support multiple port personalities with fewer structural changes. That translates into simpler manufacturing flow, better reuse of signal-integrity validation, and cleaner support for field-upgradable designs. The reduction in design branching is often the hidden economic advantage.

The part is also well matched to modular equipment where channel direction may not be known until deployment. In a frame-based system, a card may be assigned as an ingest module in one installation and as a playback or distribution module in another. A configurable SDI port allows the same hardware to support that shift with a control-plane change rather than a board respin. This is one of the rare cases where analog integration directly improves system software flexibility. That interaction between analog front-end design and platform configurability is easy to overlook, yet it is increasingly important in equipment intended for long service lives.

From an engineering perspective, the strongest positioning of the LMH0387 is not “two functions in one chip” but “direction-agnostic SDI edge design.” That distinction matters. Integration alone is common. What is less common is integration that changes how a port is architected at the system level. The LMH0387 effectively decouples connector role from fixed hardware assignment. Once viewed in those terms, its fit in digital video servers, modular gear, and multi-role broadcast equipment becomes more obvious. It supports designs where hardware standardization is a priority and per-port flexibility has measurable operational value.

There are also practical implementation implications. When using a configurable SDI I/O device, control logic and fail-safe behavior deserve careful planning. A port that can be either an input or an output should not be allowed to enter ambiguous states during power-up, reset, or software transition. In systems with multiple BNCs, deterministic default direction is important to prevent contention, misrouting, or maintenance confusion. It is generally better to define a conservative startup mode and apply role changes only after the clocking and signal-routing domains are stable. This is one of those design details that rarely appears in product overviews but often determines whether a flexible interface feels reliable in deployed equipment.

Thermal and density considerations also become more favorable with this kind of integration. Combining equalizer and driver functions can reduce component count, shorten critical analog paths, and simplify local power partitioning around each SDI connector. In dense multiport designs, every reduction in perimeter circuitry helps with placement around the mechanically constrained BNC region. That said, integration should not be mistaken for immunity to analog coupling. Adjacent SDI channels can still influence one another through supply noise, reference-plane discontinuities, and connector-field congestion. The usual high-speed discipline still applies: short paths, controlled impedance, clean return current, and careful isolation of noisy digital control signals from the analog launch and receive zones.

For applications such as distribution amplifiers and codec platforms, the LMH0387 can also reduce asymmetry between product development and product maintenance. A more uniform port design tends to make diagnostics easier because each connector can be treated as an instance of the same hardware block rather than as a unique receive-only or transmit-only path. That consistency improves test strategy and often shortens bring-up time. In experience with SDI hardware, many integration issues arise not from the serializer or deserializer core but from the analog edge conditions around the connector. Standardizing that edge with a configurable device can reduce the number of failure modes that have to be chased across product variants.

In market terms, Texas Instruments positions the LMH0387 for broadcast and professional video systems that need coax-based SDI connectivity without committing each connector to a fixed role. That positioning is sound because the device aligns best with platforms where connector flexibility produces tangible architectural gains. It is less about replacing two discrete components in isolation and more about enabling a reusable SDI interface template. For systems spanning SD, HD, and 3G-SDI, that template supports both technical compatibility and product-line efficiency. The result is a component that sits at the intersection of analog signal conditioning, connector-level configurability, and system-level hardware reuse, which is precisely where many modern video designs need leverage.

LMH0387 core architecture and configurable input/output concept

The LMH0387 is built around a port-reuse architecture in which a single external coax interface, exposed at the BNC_IO pin, can be mapped either to the receive signal chain or to the transmit signal chain. This is not just a packaging convenience. It is the central architectural decision that changes how SDI hardware can be partitioned at the board level. Instead of fixing each BNC as permanently tied to an equalizer or a cable driver, the device allows the same physical connector to serve as an input or an output under configuration control. In systems that must support multiple signal-flow topologies, this removes a layer of board-level rigidity and makes I/O assignment a configuration problem rather than a routing constraint.

At the internal signal-path level, the LMH0387 contains two functionally distinct front ends sharing the same coax-facing node. One path is the adaptive equalizer, intended to recover attenuated and frequency-shaped SDI signals arriving over coaxial cable. The other is the cable-driver path, intended to launch a controlled-amplitude serial signal back onto that same medium. The practical value of this arrangement appears in designs such as compact routers, reconfigurable monitors, test gear, and modular broadcast interfaces, where a port may need to alternate between ingest and source roles without changing the physical interconnect scheme. In these cases, the shared BNC model reduces connector specialization and simplifies front-panel planning.

When configured as a receiver, the LMH0387 routes the signal from BNC_IO into its adaptive equalizer. The equalizer compensates for the cable-induced high-frequency loss that distorts SDI eye shape over distance. From an engineering perspective, this matters because coax loss is strongly frequency-dependent. The higher spectral components of the serial stream are attenuated more than the lower components, which compresses edge rate, reduces timing margin, and closes the eye. The equalizer effectively applies the inverse trend, restoring usable amplitude balance across the signal spectrum so that downstream logic can recover the data with improved margin. In practice, this shifts the design focus away from raw connector reach and toward overall channel quality, since the equalizer can recover substantial loss but still depends on disciplined impedance control, connector integrity, and clean board transitions.

The receiver-side output interface is provided as an internally terminated 100-Ω LVDS path. This is an important implementation detail because it reduces the number of external termination decisions that can otherwise create layout inconsistency or impedance discontinuities. Internal termination shortens the list of sensitive placement items around the receive output and makes the connection into an FPGA, reclocker, or deserializer more predictable. In dense designs, this tends to improve repeatability across board revisions because fewer external passives are left to routing compromise. It also helps during bring-up, where one common failure mode in high-speed interfaces is not a core logic issue but a small termination or placement error at the boundary between analog signal recovery and digital capture.

The configurable output common-mode voltage and swing in equalizer mode add another level of interface control. These settings allow the recovered differential output to be matched more cleanly to the electrical expectations of the downstream receiver. That flexibility is often more valuable than it first appears. In mixed-vendor signal chains, nominally compatible LVDS-class interfaces can still show differences in preferred common-mode region, sensitivity to amplitude, or margin behavior under temperature and supply variation. Having programmable output characteristics allows the designer to tune interoperability rather than relying on a single fixed operating point. In development, this often shortens the path to stable eye margins when the downstream device behaves correctly in theory but shows reduced tolerance in a real board environment.

When configured as a transmitter, the LMH0387 accepts differential serial input data and routes it through the cable-driver path to the same BNC_IO node. The device then launches the SDI signal onto the coax with output characteristics suited to broadcast transport. This transmit-side mode is where the shared-port architecture becomes especially powerful. A board can expose a connector whose role is assigned late in the design cycle, or even changed across product variants, without requiring different analog front-end hardware. That can reduce SKU fragmentation and allow one PCB to cover several system roles with only configuration, assembly options, or firmware-level mode selection.

The selectable slew-rate control in cable-driver mode is more than a generic signal-integrity feature. It is a mechanism for balancing edge sharpness against channel stress, electromagnetic emissions, and overshoot behavior. Fast edges support timing fidelity, but unnecessarily aggressive transitions can amplify reflections and worsen radiated or coupled noise, especially where connector launches, vias, and reference-plane transitions are less than ideal. Slew-rate selection provides a practical tuning knob during validation. In clean coax paths, a faster setting may maximize eye opening at the far end. In more constrained assemblies, a slightly reduced edge rate often yields a better overall link because it lowers ringing and improves waveform discipline at the launch point. This is one of those cases where the best setting is rarely the most aggressive one.

A major integration advantage of the LMH0387 is the built-in return-loss network. In conventional SDI interface design, achieving SMPTE-compliant return loss often requires external compensation components carefully chosen around the connector and line interface. By integrating this network, the device removes a nontrivial analog matching task from the board designer. That has two effects. First, it reduces BOM count and routing congestion. Second, it improves consistency, because return-loss performance becomes less sensitive to external component tolerance, placement spread, and layout-induced parasitics. In compact layouts, this is often the difference between a straightforward implementation and an extended tuning cycle involving multiple passive-value iterations. The integration does not eliminate the need for disciplined RF layout, but it substantially narrows the problem space.

The system-level consequence of this architecture is a cleaner separation between signal-role definition and physical connector allocation. In fixed-function devices, the front-panel map is usually constrained early by which IC pins are input-only and which are output-only. The LMH0387 relaxes that coupling. One coax connector can be treated as a configurable SDI endpoint, and the final behavior can be determined by product mode, daughtercard population, or software-controlled operating state. This can simplify platform design in systems where the same hardware must serve as a receiver in one deployment and a transmitter in another. It also supports more efficient use of board area, because fewer dedicated signal-conditioning channels are stranded in underused roles.

There is also a subtle reliability benefit in this kind of integration. Every removed external network, especially around a high-speed coax interface, removes a source of impedance discontinuity, assembly variation, and field-debug ambiguity. In practice, many SDI issues that appear to be protocol problems are actually analog boundary problems: connector footprint mismatch, poorly placed return-loss components, stubs from test access, or a launch geometry that looked harmless at schematic level. A device that internalizes more of the analog conditioning path reduces the number of places where these errors can accumulate. This is one reason highly integrated interface parts often provide disproportionate value in dense or modular products, even when their basic function could be replicated with more discrete circuitry.

From a design strategy perspective, the most useful way to think about the LMH0387 is not as a simple equalizer-plus-driver device, but as a configurable coax endpoint with embedded compliance-oriented analog infrastructure. That framing better captures its real system value. The adaptive equalizer addresses channel loss on ingress. The cable driver manages compliant signal launch on egress. The shared BNC_IO pin turns a fixed connector into a role-flexible interface. The internal termination and return-loss support reduce the analog burden around the digital transport path. Together, these features allow the board designer to spend less effort on reconstructing standard SDI front-end circuitry and more effort on how the port behaves within the larger signal-routing architecture.

This is particularly relevant in modern compact broadcast hardware, where board area, connector density, and product variation pressure are all high. In that environment, the most valuable components are often not the ones with the longest feature lists, but the ones that collapse multiple sensitive implementation tasks into a predictable, configurable block. The LMH0387 fits that pattern well. Its architecture reduces external analog dependency, makes port direction more fluid, and provides enough electrical tuning to adapt the device cleanly into real systems rather than only idealized reference designs.

LMH0387 supported standards, data rates, and signal reach

The LMH0387 is designed to cover a wide span of SDI transport requirements with a single receive and cable-drive platform. In receive mode, it supports serial data rates from 125 Mbps to 2.97 Gbps. In cable-driving mode, it operates from DC to 2.97 Gbps. This matters at the system level because it allows one device to bridge legacy low-rate links, standard-definition SDI, high-definition SDI, and 3G-SDI without partitioning the design around multiple PHY variants. In mixed-format equipment, that directly reduces BOM fragmentation, validation overhead, and edge-case behavior between speed grades.

Its standards coverage includes ST 424, ST 292, ST 344, and ST 259, with additional support for DVB-ASI at 270 Mbps. That standards set is not just a checklist item. It defines how broadly the device can be deployed across routing, monitoring, conversion, distribution, and acquisition equipment. In practice, products often need to tolerate unpredictable operating environments where link format is determined by upstream infrastructure rather than by the local design. A receiver with this range is easier to integrate into systems that must remain format-agnostic at the physical layer.

The data-rate span also reveals an important architectural advantage. At the low end, 125 Mbps receiving capability provides margin for non-SDI serial transport cases and rate-diverse infrastructure behavior. At the high end, 2.97 Gbps support covers 3G-SDI operation, where channel loss, rise/fall-time degradation, and return-loss sensitivity become much more demanding. Supporting this entire range in one device implies that the internal equalization and output path have to remain stable across very different jitter spectra, signal amplitudes, and cable-loss profiles. That kind of wideband robustness is often more valuable than raw top-end speed alone.

For cable performance, the most operationally useful specification is equalization reach. The LMH0387 is specified to equalize up to 120 meters of Belden 1694A at 2.97 Gbps, 200 meters at 1.485 Gbps, and 400 meters at 270 Mbps. These numbers align with expected coax behavior. As the serial rate increases, channel attenuation rises, high-frequency energy is reduced more aggressively, and the eye opening at the receiver collapses faster with distance. Equalization compensates for this frequency-dependent loss, but it cannot fully defeat the physics of coaxial media. Reach therefore decreases as data rate increases, even when the cable type remains fixed.

That relationship is important when translating a datasheet into deployment limits. A quoted equalization distance is not merely a cable number. It is the end result of insertion loss, connector quality, impedance discontinuities, launch amplitude, jitter tolerance, and board-level implementation. In well-controlled lab conditions, the stated reach may be straightforward to achieve. In installed systems with multiple patch points, aging coax, marginal BNC terminations, or poor grounding continuity, usable margin can shrink noticeably. For that reason, experienced designers usually treat equalization reach as a planning ceiling, not as a target operating point. Leaving margin below the maximum published distance tends to produce more stable field behavior.

The 120-meter specification at 2.97 Gbps is especially meaningful because 3G-SDI links push coaxial transport into a regime where every discontinuity matters. A short run with several connectors can sometimes stress the receiver more than a longer continuous cable because reflections distort the waveform in ways that equalization does not fully remove. In this region, return loss and launch integrity become nearly as important as nominal cable attenuation. That is one reason why two systems using the same cable length can show very different jitter performance.

At 1.485 Gbps, the 200-meter reach provides solid headroom for HD-SDI paths common in studio infrastructure, camera feeds, and monitor distribution. This is often the range where designers get the best tradeoff between bandwidth and cable tolerance. The channel is demanding enough to require serious equalization, but still forgiving compared with 3G-SDI. Many products spend most of their service life here, even when marketed as 3G-capable. A device that performs cleanly at 1.485 Gbps with good margin often proves more valuable in real installations than one optimized narrowly for peak-rate compliance.

At 270 Mbps, the 400-meter reach reflects the much lower high-frequency loss burden of SD-SDI and DVB-ASI transport. This makes the LMH0387 useful in facilities that still carry long legacy runs or where infrastructure upgrades occur gradually rather than all at once. Supporting DVB-ASI at 270 Mbps is particularly practical because video-adjacent transport networks do not always follow a pure SDI migration path. Equipment at the edge of a system may need to interoperate with both broadcast video and transport-stream distribution, and a PHY that tolerates both reduces integration friction.

From a product-family perspective, the LMH0387 enables a unification strategy. Instead of assigning separate receive devices for ST 259, ST 292, and ST 424 classes, one part can often support the full portfolio. That simplifies PCB reuse, firmware assumptions, production test coverage, and spare-part handling. It also makes it easier to design modular platforms where I/O cards, backplanes, or daughterboards are reused across SKUs with different feature sets. This kind of device-level standardization usually creates more long-term value than the immediate component count suggests.

The cable-driving range from DC to 2.97 Gbps extends this flexibility further. DC coupling on the transmit side is useful because not every downstream path behaves like a narrow standards-only SDI link. Some systems need to preserve low-frequency content or support signal-conditioning schemes outside a strict AC-coupled assumption. A driver that remains usable down to DC gives more latitude in path design, especially in test equipment, format adaptation blocks, or custom transport sections.

There is also a practical design lesson in the way receive range and cable-drive range are specified separately. Receiver equalization is fundamentally solving a degraded-channel problem. Cable driving is solving a launch-quality problem. Treating them as symmetric functions is a common mistake. A strong cable driver cannot compensate for a weak receive margin somewhere else in the chain, and an excellent equalizer cannot recover from severe source-side waveform corruption introduced upstream. The best system behavior comes from balancing both ends: controlled output swing, clean impedance environment, minimal discontinuities, and enough equalization margin at the receiver.

For engineers selecting the LMH0387, the main takeaway is not only that it supports multiple standards and rates. It is that the device is well positioned for mixed-format coax systems where format agility, installed-cable tolerance, and platform reuse matter more than optimizing around one narrow operating point. Its published reach on Belden 1694A provides a practical anchor for channel budgeting, while its broad standards support makes it suitable for equipment that must survive real infrastructure diversity rather than idealized single-format deployment. In that sense, the LMH0387 is less a single-speed SDI component and more a flexible physical-layer building block for broadcast and professional video systems.

LMH0387 input-mode equalizer capabilities and receiver-side benefits

When the LMH0387 is configured with the BNC path as an input, it operates as an adaptive cable equalizer for serial digital video links. In this role, the device compensates for frequency-dependent attenuation introduced by coaxial cable and reconstructs the incoming signal so downstream logic sees a cleaner eye opening with improved timing margin. This function is especially valuable in SDI signal chains, where long cable runs suppress high-frequency content first, causing amplitude loss, edge-rate degradation, and increased deterministic jitter before complete carrier loss occurs.

The equalizer is adaptive rather than fixed. That distinction matters in practical systems. A fixed equalization profile may work well over a narrow cable-length window, but installed infrastructure rarely stays inside a clean design envelope. Patch fields, mixed cable vintages, undocumented adapters, and route changes all shift insertion loss. An adaptive equalizer tracks these variations and applies the amount of compensation needed to restore the serial stream over a wider operating range. In effect, the LMH0387 closes part of the channel budget at the receiver, reducing sensitivity to cable-dependent loss without requiring manual tuning.

At the signal interface level, the recovered equalized output is presented as differential LVDS on the serial data outputs. This is more than a simple logic-format conversion. Differential signaling lowers susceptibility to common-mode noise, reduces ground-referenced disturbance, and improves compatibility with high-speed FPGA inputs or external deserializers. The programmable differential output swing and programmable common-mode voltage add a useful degree of receiver-side control. In dense boards, this flexibility often determines whether the interface behaves as a nominal link or a robust one. Small adjustments in output amplitude can improve eye height at the receiving device, while common-mode tuning helps align the signal with the downstream input structure, particularly when trace loss, via discontinuities, or package effects begin to erode margin.

This programmability is often underestimated. In many video platforms, the equalizer itself is not the limiting element; the short PCB segment between equalizer and FPGA becomes the next weak point. If that interconnect includes layer transitions, connector stubs, or poor return continuity, the recovered signal can lose margin again immediately after equalization. Being able to tune output level and common-mode voltage allows the designer to compensate for that local board environment instead of treating the equalizer output as electrically fixed. In practice, this can avoid unnecessary signal-conditioning stages and simplify timing closure around the receiver.

The LMH0387 also provides status visibility that is directly useful for receiver management. Carrier detection is exposed on the CD pin, with a high level indicating that no valid input signal is detected on BNC_IO and a low level indicating that an input is present. This allows the system controller to distinguish between an idle port and an active transport stream without requiring heavier protocol-level supervision. The CDTHRESH pin supports threshold adjustment for carrier detect sensitivity; in standard implementations it can be left open or tied to ground. That default behavior is convenient, but the threshold feature becomes valuable when the installed environment is electrically noisy or when system-level policy requires tighter qualification of weak or marginal inputs.

Cable length indication adds another layer of operational intelligence. Equalization is often treated as a black box, but exposing channel-related information gives the host system a way to infer installation conditions. In modular or field-serviceable equipment, that information can support fault isolation. A port that repeatedly reports long-cable behavior with intermittent carrier loss may indicate excessive route length, degraded connectors, or a patching issue rather than a source-side fault. This kind of receiver-side observability shortens debug time because it connects electrical behavior to likely physical causes.

Power behavior is another strong receiver-side benefit. The LMH0387 reduces power consumption by automatically shifting equalization stages when cable length is 120 meters or less on Belden 1694A. This is a practical design choice because shorter links do not require the same high-gain high-frequency compensation as long links. Maintaining full equalization strength across all cases would waste power and add unnecessary thermal load. By scaling equalizer activity to channel conditions, the device aligns its internal effort with actual link demand.

The current profile reflects this adaptive strategy. Typical supply current in equalizer mode is about 71 mA for cable lengths up to 120 meters, rising to roughly 91 mA to 113 mA for cable lengths greater than 120 meters, and dropping to about 11 mA in power-save sleep mode when TX_EN is low. These numbers matter beyond simple consumption accounting. In multiport equipment, aggregate receiver power directly affects thermal density, airflow requirements, regulator sizing, and long-term reliability. A design with many front-end channels can shift from manageable to thermally constrained with only a few tens of milliamps per port. For that reason, the LMH0387’s dynamic power behavior is not just a feature; it influences enclosure design and system scalability.

This becomes particularly relevant in platforms where every BNC may be user-configurable and not all ports are active at the same time. Routers, multiformat monitors, modular DA frames, and hybrid gateway equipment often populate many receiver-capable ports to maximize flexibility, even though actual simultaneous usage is much lower. In that environment, a receiver that can idle efficiently and avoid over-consuming on short links creates a measurable system-level advantage. It reduces wasted thermal headroom and makes port density easier to scale without overbuilding the power subsystem.

A subtle but important benefit is that adaptive equalization and adaptive power behavior work together. Good receiver design is not only about recovering a signal under worst-case attenuation. It is also about doing so proportionally, without forcing every port to operate at worst-case cost. The LMH0387 reflects that balance well. It restores degraded SDI inputs, exposes enough status information for supervisory control, and provides output tuning that helps bridge the gap between analog channel recovery and digital device interfacing. That combination is often more useful than maximizing any single specification in isolation.

From an implementation perspective, the cleanest results usually come from treating the equalizer output path as part of the receiver channel, not as a separate digital domain that can be routed casually. Short differential routing, controlled impedance, tight pair skew, and a clean return path remain important after cable equalization. The device can recover lost high-frequency content from the coax, but it cannot compensate for poor board-level interconnect decisions made immediately afterward. Designs that preserve this continuity tend to extract the full benefit of the programmable LVDS interface and maintain better margin across process, voltage, and temperature variation.

Taken together, the LMH0387’s input-mode equalizer capability is valuable not only because it restores attenuated serial video signals, but because it integrates recovery, interface adaptability, signal presence monitoring, and power-aware operation into a single receiver-side function. That makes it well suited for SDI equipment where link conditions vary, downstream logic requirements are not identical across designs, and power density is as important as signal integrity.

LMH0387 output-mode cable driver capabilities and transmitter-side benefits

The LMH0387 integrates a transmit-capable SDI cable driver that is optimized for launching serial digital video directly onto 75-Ω coax through the BNC_IO pin. When TX_EN is asserted high, the device switches into output mode and the BNC_IO node becomes the active line-driving interface. In this state, the part is not simply buffering logic data. It is shaping, scaling, and conditioning a high-speed serial waveform so that the transmitted signal meets SDI amplitude and edge-rate expectations at the cable interface. That distinction matters in practice, because SDI compliance is determined at the electrical output, not at the internal logic boundary.

The transmit path accepts differential serial data at the SDI and SDI inputs. Internally, the device converts that differential input into a controlled single-ended output suitable for coaxial transport. This architecture is useful in mixed-signal video hardware because the upstream serializer or processing ASIC can remain in a differential domain, while the LMH0387 handles the impedance-facing task of driving the cable. That separation reduces the burden on the source device and usually improves overall signal integrity, especially when the serializer is not intended to directly drive a backplane connector or external coax launch structure.

Output amplitude is set through the RREF pin by means of an external resistor tied to VCC. A nominal 715-Ω resistor establishes the standard operating point. With RREF = 715 Ω ±1%, the typical BNC_IO swing is 800 mVp-p, and the specified range is 720 mVp-p to 880 mVp-p. From an engineering standpoint, this resistor is doing more than selecting a voltage level. It defines the output current scaling of the cable driver, which directly affects launch amplitude into the transmission path. In SDI systems, that amplitude window is tight enough that resistor tolerance, supply quality, layout parasitics, and output return path quality all influence the final margin. Using a 1% resistor is not merely a datasheet formality; it is a practical requirement if repeatable channel-to-channel behavior is expected across production.

The most strategically valuable transmitter feature is the selectable slew-rate control exposed on the SD/HD pin. This allows the same hardware platform to tailor output edge transitions to the active SDI standard instead of forcing one fixed edge profile across all operating modes. When SD/HD is low, the output rise and fall times are aligned with ST 424 / ST 292 operation for 3G-SDI and HD-SDI. When SD/HD is high, the output edge rates shift to satisfy ST 259M requirements for SD-SDI. This is a highly practical design choice because edge speed should track channel bandwidth and signaling rate. If edges are too slow for high-rate formats, eye opening collapses and timing margin erodes. If edges are unnecessarily fast at lower rates, the system pays for bandwidth it does not need in the form of increased overshoot, higher radiated energy, stronger sensitivity to connector discontinuities, and more visible layout-induced waveform distortion.

That tradeoff is often underestimated. In coaxial video links, many signal-integrity failures are not caused by insufficient driver strength but by excess edge energy interacting with a non-ideal launch, imperfect return path, or a marginal connector transition. A selectable slew-rate driver addresses this directly. It gives the design a controlled way to place just enough high-frequency content onto the line for the target format, rather than maximizing edge speed and hoping the interconnect absorbs the penalty. In multi-format equipment, this usually yields a more robust output stage than a one-size-fits-all transmitter.

The benefit becomes clearer when viewed from the channel outward. At the device level, the LMH0387 controls amplitude and transition rate. At the board level, those two parameters define how strongly the output excites package inductance, via stubs, connector discontinuities, and local impedance errors. At the cable level, they affect attenuation tolerance, jitter transfer, and the received eye shape after propagation. A transmit driver that is electrically compliant but not channel-aware can still produce fragile links. The LMH0387’s mode-selectable behavior helps avoid that by aligning the launch waveform with the actual operating regime.

Power behavior is also relevant in transmitter-side design. In cable-driver mode, typical supply current is 57 mA with SD/HD = 0 and the equalizer in sleep mode, and 50 mA with SD/HD = 1 and the equalizer in sleep mode. In full loopback operation, with both transmitter and receiver enabled, typical supply current rises to 117 mA. These numbers are useful not only for regulator sizing but also for thermal planning and local decoupling design. In dense video modules, the difference between transmit-only and simultaneous receive-transmit operation can materially affect rail noise and junction temperature, particularly when several channels are placed side by side. It is generally wise to budget current from the worst-case operating combination rather than from the nominal single-mode case, especially in platforms where loop-through, reclocking, or self-test modes may be enabled through firmware.

In implementation, the transmitter-side performance is strongly influenced by a few details that are easy to miss. The RREF resistor should be placed close to the device with a clean connection to VCC, because noise or trace impedance on that reference node can modulate output behavior. The BNC_IO launch should be treated as a controlled high-frequency path rather than as a generic connector trace. Short routing, continuous reference planes, and minimal discontinuity between the driver and connector usually provide more benefit than any later attempt to compensate for a poor launch. The differential SDI input pair should also be routed with symmetry and controlled impedance so the driver is not forced to correct for upstream imbalance. Even though the output side gets most of the attention, poor input quality can appear downstream as deterministic jitter or asymmetrical edges.

In multi-format products such as distribution amplifiers, encoder outputs, camera interface cards, and modular router I/O, the LMH0387 reduces the need for separate output stages tuned to individual SDI standards. One device can support different formats on shared hardware while preserving format-appropriate edge behavior. That has a direct system-level advantage: fewer dedicated output variants, less BOM fragmentation, simpler qualification, and a cleaner migration path between SD, HD, and 3G designs. The more subtle advantage is architectural consistency. When the same transmitter footprint and control model are reused across product families, validation becomes easier because the output behavior is governed by the same small set of external conditions: TX enable state, SD/HD selection, and RREF accuracy.

There is also a broader design lesson in this device’s transmit feature set. In video interfaces, compliance is often treated as a checklist item—output swing within range, edge rate within spec, connector present, done. In reality, the strongest designs treat the cable driver as the boundary between digital logic intent and analog channel reality. The LMH0387 is effective because it exposes the parameters that matter most at that boundary: whether the driver is active, how hard it drives, and how fast it transitions. That level of control is enough to make one hardware implementation behave well across multiple SDI formats without overcomplicating the design.

For transmit applications that must launch SDI cleanly onto coax, the LMH0387 provides a balanced combination of standards-oriented electrical control and implementation efficiency. Its cable-driver mode is not just a convenience feature. It is a practical mechanism for matching signal generation to channel needs, preserving output compliance, and simplifying multi-format video hardware where board space, power budget, and interoperability all matter at the same time.

LMH0387 signal-interface pins, control pins, and external component requirements

The LMH0387 combines SDI receive and transmit functions behind a shared cable-side interface, so pin interpretation cannot be treated as a simple connectivity exercise. At board level, each signal-interface and control pin participates in mode selection, impedance control, or analog loop stability. A correct implementation depends on understanding not only what each pin connects to, but also why the surrounding external network is required.

The BNC_IO pin is the central analog I/O node for the coax interface. It connects to the BNC connector through an AC-coupling capacitor, typically 4.7 μF. This capacitor is not a formality. It isolates DC bias conditions inside the device from any external cable environment while preserving the low-frequency content needed for pathological SDI patterns. In practice, the capacitor choice should be evaluated for effective capacitance under DC bias, ESR, and package parasitics. A nominal 4.7-μF part that loses significant capacitance in operation can degrade low-frequency response and increase baseline wander margin risk. Placement also matters. The capacitor should sit close to the device-side signal path, with a short return-aware routing structure to avoid introducing unnecessary discontinuity between the IC and the connector.

Because the LMH0387 integrates both a cable equalizer and a cable driver, BNC_IO behaves differently depending on operating mode. In receive mode, it is the input node for the adaptive equalizer path. In transmit mode, it becomes the driven SDI output node. That dual use is convenient for compact designs, but it also means the inactive internal path must be managed carefully. If left floating or improperly terminated, the unused section can interact with the active path through parasitic coupling, producing reflections, eye degradation, or unexpected amplitude behavior. This is one of the places where mixed-function interface ICs reward disciplined implementation and penalize casual routing.

For equalizer operation, AEC+ and AEC- form the adaptive equalizer loop filter connection and require a 1-μF capacitor between the two pins. This capacitor is part of the control loop that allows the equalizer to adapt to cable loss across data rate and cable length variation. Electrically, it helps define loop dynamics such as response speed and stability margin. If the capacitor is noisy, poorly placed, or routed across a disturbed reference region, the equalizer can still function but may converge less cleanly under marginal cable conditions. In lab bring-up, unstable or slow equalization often traces back not to the coax itself, but to the analog quality of this loop-filter network. The shortest and most symmetric placement between AEC+ and AEC- is usually the safest approach.

The high-speed digital data path is split into differential internal-side interfaces. In transmitter operation, the incoming serial data is applied at the differential SDI inputs. In receiver operation, the recovered serial data is delivered at the differential SDO outputs. These pins sit at the boundary between the cable-domain analog front end and the logic-domain transport path. Good differential routing practice is therefore still required even though the device handles cable equalization and line driving internally. Pair matching, controlled impedance, uninterrupted reference planes, and minimized stub length remain relevant. The LMH0387 can correct cable loss; it cannot undo poor local interconnect geometry on the PCB.

The unused-path termination scheme is especially important because the device integrates two otherwise independent signal chains. TERMRX terminates the unused receiver input path. It should connect through a 1-μF capacitor and then a 220-Ω resistor to ground. TERMTX terminates the unused transmitter output path. It should connect through a 4.7-μF capacitor and then a 75-Ω resistor to ground. These networks do more than “quiet” unused pins. They create a defined AC environment that prevents the inactive circuitry from behaving like an unterminated branch off the main signal path. In SDI systems, even a short unterminated branch can introduce enough reflected energy to reduce return loss margin and distort the eye, particularly at higher rates. The specified resistor values and capacitor sizes are tuned to the function of each internal path, so substituting “close enough” values should be avoided unless validated on the bench.

A useful way to think about TERMRX and TERMTX is as isolation loads for mode-dependent internal topology. When receive mode is active, the transmitter side should not appear as a latent mismatch hanging off BNC_IO. When transmit mode is active, the receiver side should not become a partially coupled observer that injects sensitivity to common-mode disturbances or creates an unintended reflection node. This is one of the less obvious aspects of combo SDI parts: mode selection alone is not enough; inactive-path analog closure is part of the design.

The TX_EN pin defines whether the transmitter output driver is active. To configure the LMH0387 as a receiver, TX_EN must be held low, disabling the BNC_IO output driver. To configure it as a transmitter, TX_EN must be held high, enabling the driver. This pin has direct control significance, but it also has system-level consequences. If TX_EN is mishandled during power sequencing, reset, or FPGA startup, the cable interface can briefly enter the wrong electrical state. On a shared backplane or patch environment, that can appear as momentary bus contention or unexplained disturbance on the line. Since TX_EN has an internal pullup, the default behavior tends toward transmit enable unless the design explicitly overrides it. That default should be treated carefully in receiver-centric designs. A firm external pull strategy or deterministic control timing is usually preferable to relying on internal bias alone.

In transmitter mode, the receiver can be powered down through SPI sleep-mode control. This is a practical feature, not just a power-saving footnote. Disabling the unused receive chain reduces internal activity, can improve thermal distribution, and removes one more source of unnecessary analog interaction. In dense video I/O hardware, small thermal and noise improvements often accumulate into noticeably better robustness under corner conditions.

The SPI control interface consists of MOSI, MISO, SCK, SS, and SPI_EN. SPI_EN should always be high in input mode and may optionally be high in output mode. It includes an internal pulldown. SS includes an internal pullup. TX_EN includes an internal pullup. SD/HD includes an internal pulldown. These built-in bias networks are useful for reducing external component count, but they should not be mistaken for strong configuration guarantees. Internal pull devices are typically weak. They help avoid floating pins during benign conditions, but they are not a substitute for deliberate state control in electrically noisy environments or during asynchronous startup. Designs that depend heavily on internal pulls often pass schematic review yet show intermittent mode-selection errors during real power ramps, hot-plug events, or long control trace operation.

From an engineering standpoint, SPI_EN deserves extra attention because it gates the control-plane behavior of the device. If left ambiguous, debugging can become misleading: analog symptoms at the BNC may actually originate from a mis-latched digital control state. A disciplined design usually assigns every mode-relevant pin a deterministic external state, even when the datasheet permits optional reliance on internal pulls. That approach costs little and pays back quickly during board bring-up.

The supply structure is partitioned into transmitter and receiver domains. VCCTX powers the transmitter section, VCCRX powers the receiver section, and VEE is ground. The recommended operating range is 3.14 V to 3.46 V, with 3.3 V nominal. This split supply arrangement should be used as an opportunity to isolate noise, not merely as two pins tied to the same rail blob. Even when both domains come from the same 3.3-V source, local filtering and decoupling should reflect their different current signatures. The transmitter side tends to inject stronger switching and output-driver-related transients. The receiver side is more sensitive to analog front-end and equalizer stability. Shared impedance between VCCTX and VCCRX can therefore convert transmit activity into receive-domain disturbance. A quiet layout typically uses separate local decoupling clusters, short supply paths, and a low-impedance ground reference stitched tightly around the device.

Decoupling strategy should include multiple capacitor values placed close to each supply pin group to cover a broad frequency range. The smallest capacitors should be located with minimum loop area, while bulk support should be close enough to maintain local energy availability without forcing high di/dt currents through long traces. In practice, supply integrity issues in SDI interface devices often show up as output amplitude variation, jitter sensitivity, or equalizer instability long before they appear as obvious DC voltage problems.

At the application level, these pin and component requirements define three interacting layers of design. The first layer is electrical correctness: AC-coupling values, loop-filter capacitor, unused-path terminations, and legal supply voltage. The second layer is signal integrity: controlled routing, connector transition quality, minimized discontinuities, and clean grounding. The third layer is operational determinism: TX_EN behavior, SPI state control, and power-down management of inactive functions. Designs that satisfy only the first layer usually operate under nominal conditions. Designs that satisfy all three layers remain stable across cable variation, startup sequencing, and real deployment noise.

A strong implementation of the LMH0387 therefore treats the device as a compact SDI analog subsystem rather than a simple pin-compatible transceiver. The recommended capacitors and terminations are not peripheral details; they define the analog boundary conditions the internal equalizer and driver expect. When those conditions are preserved, the shared BNC interface behaves predictably in both directions, mode transitions become cleaner, and board-level validation becomes much more straightforward.

LMH0387 SPI control, programmability, and functional modes

The LMH0387 is more than a fixed SDI physical-layer device. Its SPI interface turns several analog operating points into configurable parameters, which materially changes how the part can be deployed in real systems. Instead of accepting a single factory-defined compromise between reach, swing, power, and interoperability, the design can be tuned at board level and, if needed, at system level. That flexibility is most valuable in equalizer mode, where channel behavior depends strongly on cable type, connector quality, trace discontinuities, and the actual data-rate mix seen in the field.

At a functional level, the SPI path exposes control over output common-mode voltage, output swing, launch amplitude behavior, cable-length-related operating characteristics, sleep settings, and extended 3G reach features. These are not cosmetic options. They alter the signal-conditioning profile of the device and therefore influence eye opening, jitter tolerance, interoperability margin, and in some cases system power posture. In practice, this means the LMH0387 can be tuned for a specific channel rather than forcing the channel to fit a fixed receiver behavior.

The most important point is that equalization performance is never purely a datasheet number. Cable reach is shaped by insertion loss, return loss, connector transitions, PCB launch quality, and the statistical distribution of source amplitudes. A programmable equalizer is therefore more useful than a nominally similar fixed-function device because it allows the operating point to be aligned with the actual channel population. In deployments where installed coax differs across sites or where patch-panel density introduces additional reflections, the ability to shift behavior through SPI often creates more practical value than a small improvement in headline reach.

The extended 3G reach setting is a good example of this design philosophy. Enabling this mode increases cable reach at 3G-SDI rates, but the gain is not free. The device reallocates its equalization behavior in a way that reduces achievable margin for HD and SD operation. From an engineering standpoint, this is a bandwidth-prioritization trade. The channel compensation is being biased toward the higher-loss region associated with 3G signaling, and that optimization naturally moves the response away from what is ideal for lower-rate formats. The key issue is not simply whether extended reach works, but whether the full format envelope of the target product still closes with adequate margin after the change.

That trade should be evaluated against the real application rather than against abstract capability tables. In a 3G-only production chain with controlled source equipment and known cable classes, enabling extended 3G reach can be the correct decision because the sacrificed HD and SD margin has no operational value. In a router, monitor, or infrastructure product expected to accept mixed-format feeds, the same setting can become a latent interoperability risk. Systems that look stable in a bench setup with fresh cable assemblies may show unexpected edge sensitivity once aged connectors, long patch paths, or low-amplitude sources are introduced. In that kind of environment, preserving wider multi-rate margin is often more valuable than extracting the last increment of 3G distance.

Programmable output common-mode voltage and output swing add another important dimension. These controls affect how the LMH0387 presents its signal to the next stage and can be used to improve compatibility with downstream receivers, serializers, or crosspoint inputs. The benefit is not only compliance tuning. Adjusting common-mode and swing can help reduce downstream overdrive, improve eye symmetry at the receiving node, and compensate for losses or loading introduced by board-level interconnect. In dense layouts, small changes in launch conditions can noticeably affect measured eye quality after several inches of trace, especially when vias and connector transitions are involved. A configurable output stage helps recover margin without a board respin.

Launch amplitude optimization should be understood as part of the channel, not as a local parameter isolated to the transmitter side of the device. The launched waveform interacts with trace impedance, package parasitics, connector discontinuities, and receiver threshold behavior. If amplitude is too low, the equalized signal may fail to maintain adequate noise margin at the far end. If too high, overshoot and deterministic jitter can increase, especially in channels with strong reflections. The practical target is usually not maximum amplitude, but the cleanest eye at the receiving interface under worst-case process, voltage, temperature, and cable conditions. That distinction matters because aggressive settings that look best on a short lab fixture may perform worse on long or reflection-prone channels.

Sleep-mode configuration through SPI is operationally simpler but still strategically useful. In modular or multi-channel systems, selective power reduction can be coordinated by firmware based on signal presence, operating mode, or service state. This improves platform efficiency and thermal distribution without changing the hardware design. The main engineering value is control granularity: channels that are inactive can be placed into a lower-power state while active links retain optimized settings. In equipment with many SDI paths, that can reduce aggregate dissipation enough to ease enclosure thermal constraints or fan policy.

The SPI timing itself is straightforward and fast enough for configuration-oriented use. The interface supports SCK frequencies up to 20 MHz, with 4 ns minimum setup and hold timing for MOSI and slave-select relationships, 10 ns minimum slave-select off time, and 15 ns maximum timing for MISO output enable, disable, and delay behavior. These numbers indicate a conventional high-speed peripheral interface rather than a runtime control bus intended for cycle-by-cycle adaptation. In practice, this means SPI writes are best treated as deterministic configuration transactions performed during initialization, mode switching, fault recovery, or controlled recalibration events. It is technically possible to reprogram dynamically, but stability is usually improved when register updates are tied to explicit operating-state transitions rather than frequent opportunistic changes.

That usage model has an important architectural implication. Because the analog front end becomes software-configurable, a single PCB can support multiple product personalities. One firmware image may favor maximum 3G reach for long-haul point links. Another may prioritize broader multi-format tolerance for infrastructure nodes. A third may alter output characteristics to match a different downstream interface environment. This reduces the need for hardware variants and shifts optimization into configuration management, which is typically cheaper to validate and easier to maintain than a family of slightly different board designs.

From a platform perspective, this is where the LMH0387 becomes especially attractive. Procurement complexity decreases because one qualified device can cover a wider operational envelope. Manufacturing flexibility improves because late-stage feature differentiation can be handled by register settings. Field support also benefits: if a deployed system encounters a cable environment that was not fully represented during qualification, there is at least some ability to recover margin through firmware rather than requiring physical redesign. That does not eliminate the need for careful SI validation, but it creates a meaningful buffer against installation variability.

The most effective way to use the SPI features is to treat them as part of a structured signal-integrity workflow. Start with a baseline configuration that is conservative across all required data rates. Characterize eye quality, jitter, and lock robustness using representative short, medium, and long channels. Then adjust one parameter group at a time—reach mode, output level, common-mode, power state—and observe not only whether the primary metric improves, but whether a secondary mode regresses. This matters because SDI links often fail first at the corners: marginal source amplitude, long cable, a poor connector pair, and a temperature-shifted receiver. Configuration that appears optimal in isolation can narrow total system margin when those effects stack.

A practical pattern is to define validated register profiles rather than allowing unrestricted tuning in production code. For example, a profile can be qualified for 3G-only long-reach operation, another for mixed-rate infrastructure use, and another for short controlled backplane or internal cabling environments. This keeps the flexibility of programmability while preventing accidental drift into poorly characterized combinations. It also makes bring-up and field diagnostics much cleaner because behavior can be tied to known configuration states instead of ad hoc register changes.

In effect, the LMH0387 SPI interface converts analog equalizer behavior into a manageable design variable. That is its real value. The device still depends on the fundamentals of channel loss and impedance control, but it gives the system designer a way to move the operating point after the board is built. For SDI systems that must survive cable diversity, product-line segmentation, and evolving deployment conditions, that is often the difference between a part that merely functions and one that can be engineered into a robust platform.

LMH0387 electrical characteristics, power behavior, and thermal conditions

The LMH0387 is best understood as a mixed-signal SDI interface device whose electrical limits, signal-conditioning behavior, and thermal profile are tightly coupled. Its nominal operating point is a single 3.3 V rail, with a recommended range of 3.14 V to 3.46 V. That range looks conventional, but in practice it defines the margin available for output swing, internal equalization accuracy, clock-data path stability, and logic threshold integrity. In compact broadcast or video-routing hardware, supply droop from shared backplanes, hot-swap events, or simultaneous switching can consume that margin quickly. For this device, stable 3.3 V distribution is not just a power requirement; it is part of signal integrity control.

The industrial temperature range of -40°C to 85°C extends its usability well beyond controlled indoor installations. This matters because SDI paths often sit near FPGAs, crosspoints, reclockers, and power converters, where local heating is uneven and often underestimated during bench validation. A device may remain within absolute temperature limits while still experiencing measurable performance drift if airflow is poor or the local copper plane is thermally fragmented. In systems with multiple always-active channels, thermal gradients across the board can become more relevant than average ambient temperature. That is one reason why thermal behavior should be evaluated under realistic routing density and steady-state traffic, not only under open-bench conditions.

The logic interface is straightforward but deserves careful interpretation. A logic high input is specified from 2 V up to VCC, while a logic low input spans from VEE to 0.8 V. Output high is guaranteed at 2.4 V minimum with a -2 mA load, and output low is 0.4 V maximum with a 2 mA load. These thresholds indicate conventional digital compatibility, but the more important engineering implication is noise margin under mixed-domain operation. When the LMH0387 is controlled by programmable logic running at lower I/O standards or through long traces in electrically noisy regions, threshold headroom can narrow. It is usually safer to treat control-path cleanliness with the same discipline applied to the high-speed data path, especially where mode pins affect equalization or driver behavior dynamically.

In equalizer mode, the device is intended to recover degraded incoming SDI content after cable loss. At 0-meter cable length, the typical input swing is 800 mVp-p, and the differential receiver output is typically 700 mVp-p with a typical output offset of 1.25 V. Those numbers suggest a signal path optimized for high-speed differential interfacing rather than generic logic-level translation. The output common-mode behavior matters because it affects downstream termination, AC-coupling strategy, and eye opening at the next stage. Designers often focus only on recovered amplitude, but offset voltage and load environment are equally important in preserving a clean transition region.

The specified rise and fall times at the differential equalizer output, typically 80 ps to 130 ps with a 100 Ω load, indicate a very fast edge environment. At these transition rates, board parasitics stop being secondary effects and start shaping the waveform directly. Stub length, via discontinuity, reference-plane interruption, and imperfect differential impedance all translate into visible edge distortion or deterministic jitter. A common lab observation is that a path appearing acceptable at lower SDI rates can develop output asymmetry or reduced eye height when pushed toward 2.97 Gbps, even though the IC remains fully within datasheet conditions. In many cases the limiting factor is not the equalizer itself but the interconnect immediately after it.

In cable-driver mode, the LMH0387 supports input data rates up to 2.97 Gbps. This aligns with 3G-SDI operation and places the device in the range where additive jitter must be treated as a system budget term, not merely a component statistic. The typical additive jitter is 20 ps peak-to-peak at 2.97 Gbps, 18 ps peak-to-peak at 1.485 Gbps, and 15 ps peak-to-peak at 270 Mbps. The trend is expected: as data rate rises, jitter tolerance shrinks and every discontinuity contributes more strongly to timing uncertainty. What matters in deployment is how this additive jitter stacks with upstream source jitter, power-supply-induced modulation, connector reflections, and receiver tolerance at the far end. A design can pass isolated component checks and still fail end-to-end margin if the jitter budget is assembled too optimistically.

The cable-driver output transition time is mode-dependent. For SD/HD = 0, rise and fall time is typically 65 ps to 130 ps. For SD/HD = 1, it broadens to 400 ps to 800 ps. This distinction is more than a mode-table detail. It reflects deliberate edge-rate control to align spectral content and compliance behavior with the intended SDI format. Faster edges improve timing definition but increase high-frequency energy, making the channel more sensitive to return loss, radiation, and layout imperfections. Slower edges reduce spectral spread and can improve robustness in lower-rate operation. Edge-rate selection should therefore be treated as part of channel engineering, not merely protocol configuration.

Return loss specifications across 5 MHz to 3 GHz on both input and output paths reveal one of the most practical aspects of the device. The IC includes the internal return-loss network, but final return-loss performance remains board-dependent. This is exactly where many implementations diverge from datasheet expectations. Return loss is shaped not only by the silicon but by launch geometry, connector footprint quality, reference-plane continuity, decoupling placement near high-speed pins, and the interaction between package parasitics and transmission-line impedance. It is often tempting to assume that an integrated return-loss network guarantees compliance. In reality, it only establishes a starting point. Compliance is finished by the PCB.

That board dependence becomes especially visible during evaluation. A layout that uses nominal 75 Ω routing but includes unnecessary test pads, asymmetrical via transitions, or nearby copper voids can show degraded return loss well before the cable interface itself becomes the bottleneck. In repeated bring-up work, the most reliable results typically come from keeping the output launch short, avoiding stubs entirely, tying shield and ground strategy to the connector geometry from the start, and validating the path with TDR or VNA methods rather than relying only on eye-pattern checks. Once the return-loss issue appears in waveform capture, the root cause is often already embedded in the stackup or escape routing.

The 48-pin TLGA package with a 7.00 mm × 7.00 mm body size supports compact placement, but compact packages concentrate thermal and routing constraints into a small footprint. The thermal resistance from junction to ambient is 64.5°C/W, and junction to board is 32.3°C/W. These values do not indicate a high-power device, yet they clearly show that board-level heat extraction is meaningful. In dense designs, especially those operating continuously with loopback paths or multiple adjacent high-speed channels, even moderate power can elevate junction temperature enough to reduce margin. This is particularly true when the package sits near larger heat sources that raise local board temperature independently of the device’s own dissipation.

A practical way to read the thermal numbers is to treat the board as the primary heat sink. Junction-to-board thermal resistance being much lower than junction-to-ambient means copper quality, via field density, and local plane connectivity strongly influence final operating temperature. Sparse copper under the package or thermal isolation caused by segmentation can increase temperature more than expected from power calculations alone. In contrast, a well-stitched ground structure often yields noticeably better thermal stability without any explicit heatsink. For compact video hardware, thermal success usually comes from integrating signal integrity and thermal design early, because the same reference planes that support controlled impedance also provide the dominant heat-spreading path.

Power behavior should therefore be evaluated as a dynamic issue rather than a static supply number. High-speed mode changes, cable loading differences, output switching activity, and neighboring devices all affect local current demand and heat generation. Decoupling should be distributed across frequency ranges, with very short high-frequency paths at the package and sufficient bulk support nearby on the rail. It is also useful to separate quiet analog return paths from noisy digital current loops wherever the layout allows, even in a single-supply design, because supply contamination often appears first as jitter growth rather than outright malfunction. In devices like the LMH0387, clean power, clean reference geometry, and thermal stability reinforce each other.

Taken together, the LMH0387 electrical characteristics describe a device with solid high-speed capability, but one that rewards disciplined implementation. The datasheet values for logic thresholds, output swing, jitter, edge rate, return loss, and thermal resistance are not isolated parameters. They form a system envelope. If supply integrity is weak, edge quality and jitter suffer. If layout is careless, return loss degrades and equalizer or driver performance is masked. If thermal spreading is insufficient, operating margin narrows under sustained traffic. The strongest designs usually come from treating the part not as a drop-in SDI interface block, but as a calibrated high-frequency element whose full performance emerges only when power, interconnect, and thermal paths are engineered as one structure.

LMH0387 implementation guidance, application scenarios, and design considerations

LMH0387 implementation is most effective when it is treated not simply as an SDI interface IC, but as a role-switchable signal boundary element. Its real value appears in architectures where the physical connector assignment is not fixed early, or where multiple product variants must share the same PCB, BOM, and mechanical envelope. In that context, the device is less about basic compliance and more about preserving platform optionality while keeping the RF-facing portion of the design stable.

The most practical use case is a shared BNC node that may operate either as an SDI receive path or an SDI transmit path, depending on firmware configuration, assembly option, or SKU definition. In a modular broadcast platform, this enables one front-panel connector footprint to serve different functions across closely related products. The hardware baseline remains common, while logic, control-state handling, and population options determine final behavior. That directly reduces schematic divergence, shortens validation loops for derivative products, and lowers the number of unique assemblies that must be supported in manufacturing and service.

This flexibility becomes even more useful in equipment families that span multiple SDI rates and standards. The LMH0387 supports operation from 125 Mbps to 2.97 Gbps and aligns with ST 259, ST 292, ST 344, and ST 424. In practice, that means a single interface strategy can cover SD-SDI, HD-SDI, and 3G-SDI product tiers without forcing a redesign of the connector-side analog front end. That kind of standard coverage does more than reduce component count. It stabilizes qualification effort. Once the signal path around the BNC has been tuned and verified, the same implementation can often be carried across encoders, decoders, routers, frame synchronizers, and monitoring products with only limited adaptation.

From an implementation perspective, the device should be viewed as sitting at the intersection of three domains: transmission-line behavior at the connector, mode control inside the platform, and system-level signal-integrity policy. The schematic details matter because each supporting element around the LMH0387 is part of a calibrated interface environment rather than a generic passive recommendation.

The BNC_IO pin requires the recommended 4.7-μF AC-coupling capacitor. This capacitor is not just a blocking component. It directly participates in preserving the intended signal transfer behavior across the supported SDI rate range. Substituting a different value without analysis can shift low-frequency response, affect pathological-pattern handling, or degrade margin during edge-case cable and source conditions. In practice, designs that treat this capacitor as interchangeable often pass bench checks at nominal conditions but show weaker robustness during compliance-style stress tests or when connected to less ideal upstream equipment.

The AEC loop also requires careful treatment. The specified 1-μF capacitor between AEC+ and AEC- is part of the adaptive equalization control behavior and should be placed with short, quiet routing. This node is easy to underestimate because it does not sit in the obvious signal path, yet it strongly influences recovery behavior under cable loss and rate changes. If this capacitor is poorly placed or its grounding environment is noisy, the equalizer can become less predictable, especially at the boundary between acceptable and marginal cable conditions. A common field symptom is not complete link failure, but inconsistent lock margin between nominally identical boards.

Unused paths must be terminated with the recommended TERMRX and TERMTX networks. This is important for two reasons. First, unused high-speed analog nodes can still act as stubs, coupling points, or reflective structures if left floating or only partially constrained. Second, the internal signal-routing assumptions of the device depend on the external termination context. Properly terminating inactive paths reduces uncertainty in return loss and helps preserve clean mode transitions when the connector role changes. In mixed-use platforms, this becomes especially relevant because the same board may be deployed in both RX and TX configurations, and any shortcut taken on the unused path can show up only in one variant, making debug unnecessarily expensive.

TX_EN must be managed as a true operating-state control, not as a static strap that happens to work in a lab setup. When the BNC is configured as an output, TX_EN must place the transmit path in the intended state. When the connector is acting as an input, TX_EN must prevent the transmit section from creating contention or unwanted loading behavior. This is particularly important in systems with dynamic role assignment, remote configuration, or shared firmware across multiple product images. A robust design usually ties this control into the same state machine that governs crosspoint routing, reclocker mode, LOS handling, and front-panel labeling logic. That avoids a class of integration bugs where the digital control plane and the analog port role fall briefly out of sync during boot, reset, or mode switching.

PCB layout remains a first-order design variable even though the LMH0387 integrates return-loss optimization. The integrated network improves implementation tolerance, but it does not eliminate the need for controlled-impedance routing or careful connector launch design. The connector region should be treated as a short RF structure. Trace width, via usage, anti-pad geometry, layer transitions, and local return-current continuity all influence the effective impedance presented to the cable. If the launch is poorly executed, the integrated return-loss support cannot compensate for board-induced discontinuities. This is one of the more important practical lessons in SDI hardware: integration helps most when the remaining interconnect is already disciplined. It does not rescue an uncontrolled launch.

The area around the BNC connector deserves particular attention. Keep the route from connector to coupling capacitor and device as short and geometrically stable as possible. Avoid unnecessary branches, test pads directly on the main line, or abrupt reference-plane interruptions. If a layer transition is unavoidable, the return path through the transition must be intentionally supported. On high-volume boards, even small mechanical adjustments around the front-panel connector can shift performance enough to matter, so it is worth validating the exact assembled launch rather than assuming the schematic alone guarantees compliance.

If SPI-controlled extended 3G reach settings are used, they should be evaluated as a system tradeoff rather than a free performance gain. Extending reach at 3G can change behavior at HD and SD rates, including cable-length margin and equalization balance. The key point is that equalization optimization is not rate-neutral. A configuration that improves one operating point may reduce margin at another. In multi-standard equipment, the correct question is not whether the longest possible 3G cable can be achieved in isolation, but whether the aggregate operating envelope across SD, HD, and 3G remains acceptable for the intended deployment. That distinction matters in products expected to handle unpredictable field cabling rather than a fixed installation profile.

A useful way to structure the design process is to move through three validation layers. First, verify the static implementation against the datasheet: coupling capacitor values, AEC capacitor placement, unused-path termination, TX_EN logic, supply decoupling, and layout discipline. Second, verify signal integrity across all supported rates using representative cable lengths, pathological patterns, and both strong and weak sources. Third, verify behavioral transitions: power-up defaults, role changes, reset handling, cable hot-plug events, and firmware-controlled mode switching. Many issues with flexible SDI ports do not appear during steady-state transmission. They emerge during transitions, especially when one subsystem changes state faster than another.

For product planning, the LMH0387 is especially attractive when reducing platform fragmentation has measurable value. A single connector circuit that supports input or output assignment can simplify spare strategy, contract manufacturing flows, and revision control. Fewer front-end variants usually mean fewer exceptions in procurement and fewer opportunities for assembly error. At the same time, this advantage only materializes if the implementation is tightly aligned with the device’s intended external network. Integration shifts complexity inward, but it does not remove the need for precision around the remaining passives and board geometry.

From a sourcing and risk perspective, this device can reduce dependency on multiple specialized interface parts across a product family. That tends to improve BOM resilience and simplify qualification. However, the surrounding passive set should be treated as part of the functional solution, not as low-priority commodities. Capacitance value, dielectric behavior, tolerance, package parasitics, and placement all affect final performance. In connector-facing high-speed designs, the “main IC plus generic passives” mindset often creates preventable variation between prototypes, pilot builds, and production lots. A more reliable approach is to lock the passives, footprint strategy, and layout stack-up as a validated interface module.

In broader architectural terms, the LMH0387 fits best in systems where analog-port flexibility is worth more than the absolute simplicity of a fixed-function input or output stage. If the product line is static and every connector role is permanently defined, a simpler dedicated approach may be easier to optimize. But where a platform must support evolving feature sets, regional variants, or field-configurable I/O behavior, the LMH0387 provides leverage. It turns the BNC interface from a hardwired decision into a controlled resource. That is often the more scalable choice, especially in broadcast and professional video equipment where product reuse, standards coverage, and predictable integration effort matter as much as raw channel performance.

Potential Equivalent/Replacement Models for LMH0387

Potential replacement analysis for LMH0387 must begin with one constraint: based only on the cited LMH0387 material, no direct drop-in or explicitly named equivalent is identified. That means any replacement effort cannot start from a part-number cross table. It has to start from functional decomposition of what the device is doing at the system boundary, then work inward toward electrical, protocol, and board-level constraints.

The most critical point is that LMH0387 is not simply an SDI equalizer and not simply an SDI cable driver. Its value is in combining both roles around a shared, configurable BNC-side interface concept. That architectural detail is usually where replacement attempts fail. A candidate may match data rate and standards compliance, yet still break the original design intent because it forces the channel into a fixed receive-only or transmit-only topology. In practice, this changes connector usage, signal routing, control logic, protection strategy, and often the operator-facing behavior of the equipment.

A technically valid comparison should therefore be organized around several layers.

At the protocol and line-rate layer, the replacement must support operation through 2.97 Gbps and align with the SDI standards explicitly associated with LMH0387: ST 424, ST 292, ST 344, and ST 259. This is the baseline filter. If a device does not span the same standards set, it is not a real replacement candidate, even if it can pass one nominal bitrate in lab conditions. SDI interoperability problems often appear at edge-case pathological patterns, long cable runs, or mixed-generation infrastructure, so standards alignment matters more than a headline bitrate.

At the analog front-end layer, the replacement must replicate both equalization and cable-drive capability in one integrated solution, or provide a system-level path to preserve the same external behavior. Equalization performance alone is insufficient. Cable-drive strength alone is insufficient. The original device’s usefulness comes from allowing one physical port concept to support more than one role, which simplifies dense I/O designs and enables flexible routing products. If the substitute splits these functions across multiple devices, the design may still be recoverable, but it is no longer a like-for-like replacement. Power distribution, failure modes, control sequencing, and BOM risk all change.

At the connector-interface layer, the shared configurable BNC-side I/O model deserves special scrutiny. This is the feature that should be treated as a first-order requirement, not a secondary convenience. Many engineers initially rank equalizer metrics or output swing as the main selection criteria, but in mixed-direction SDI designs the port architecture usually drives the rest of the board decisions. Once that concept is lost, replacement cascades into enclosure changes, crosspoint mapping changes, and firmware updates for port-role management. In other words, the architecture around the connector often matters more than the signal-conditioning block in isolation.

At the signal-integrity layer, the integrated return-loss network is another nontrivial requirement. It is easy to underestimate because it appears to be a support function rather than the main signal path. In real SDI hardware, however, return loss strongly influences interoperability across cable types, patch fields, and aging infrastructure. An alternative part without equivalent integration may require external matching networks, and that introduces layout sensitivity and tuning effort. What looked like a pin-compatible electrical replacement can quickly become a board-revalidation exercise. This is especially relevant when existing products have already been tuned for compliance margins and field robustness rather than just bench-top functionality.

At the control and configurability layer, SPI programmability for equalizer-related functions should be preserved. This matters for more than register access. It affects production calibration flow, diagnostics, field service behavior, and firmware abstraction. Devices that expose only hardware straps or limited autonomous operation may appear simpler, but they reduce observability and control in systems that need adaptive behavior or detailed fault reporting. In multi-format video equipment, that programmability often becomes the difference between a board that merely works in nominal conditions and one that remains manageable across revisions, cable environments, and installed-base variations.

At the power and environmental layer, 3.3 V single-supply operation and industrial temperature support are not box-check items; they define integration risk. A part that requires additional rails can force changes in regulator headroom, sequencing, thermal density, and EMI behavior. A part limited to narrower temperature range may pass characterization but fail long-term deployment expectations, especially in sealed, rack-dense, or outdoor-adjacent systems. Replacement studies are most reliable when they assume worst-case operating corners early rather than treating them as final validation details.

At the mechanical and layout layer, package compatibility and board-level integration constraints must be evaluated with discipline. Even if a candidate meets all electrical requirements, differences in pinout, thermal pad strategy, grounding topology, or high-speed trace escape can invalidate the migration cost model. For SDI devices operating near 3 Gbps, package parasitics and layout geometry are not secondary implementation details. They shape eye opening, deterministic jitter, and cable-launch quality. A replacement that looks acceptable on a feature list may still require a full PCB spin and SI requalification.

A practical evaluation flow is to divide candidate parts into three classes. First are true architectural matches: devices that integrate equalization and cable drive while preserving a configurable shared port concept. These are the only candidates that deserve to be called near-equivalents. Second are electrical partial matches: devices that meet bitrate and standards but implement only one side of the link function. These can work only if the system is redesigned around separate receive and transmit devices. Third are nominal matches: devices that claim SDI support at similar rates but miss critical features such as integrated return-loss handling, SPI control depth, or temperature range. These usually consume the most engineering time because they look promising until late-stage validation exposes the gaps.

In board bring-up work, one recurring pattern is that partial replacements often succeed in a controlled lab setup with short coax and clean supplies, then degrade when inserted into a full signal chain with multiple patch points and marginal source amplitudes. That is why replacement analysis should not stop at static spec comparison. Attention should be given to cable equalization recovery margin, output launch quality into real 75-ohm environments, behavior across pathological patterns, and software interaction with adaptive settings. If the original design relied on LMH0387 to absorb system variability, a less integrated substitute will transfer that burden into firmware, layout, or external passives.

A disciplined sourcing team should therefore treat the LMH0387 replacement question as an architecture-preservation problem first and a component-selection problem second. The decisive criteria are:

support for both equalizer and cable-driver operation in one device

preservation of a configurable shared BNC-side I/O concept

compliance with ST 424, ST 292, ST 344, and ST 259

operation through 2.97 Gbps

integrated return-loss network or a proven equivalent implementation path

SPI programmability for equalizer-related behavior

3.3 V single-supply operation

industrial temperature capability

package, layout, and board-integration compatibility

If a candidate fails the shared-port architecture requirement, it should be treated as a redesign option, not a replacement. That distinction helps avoid a common engineering mistake: approving a substitute based on overlapping data-sheet bullets while missing the original system abstraction the part was enabling. For LMH0387, that abstraction is the real feature set.

conclusion

For engineering evaluation and sourcing decisions, the Texas Instruments LMH0387 should be assessed as a configurable SDI physical-layer building block rather than a fixed-function interface IC. It integrates adaptive cable equalization, cable driving, and output/input role assignment into a single 3.3 V device, which directly affects front-end architecture, board reuse strategy, and SKU control. The most important design implication is not only signal recovery or drive strength, but the ability to map one BNC-facing channel as either an SDI input or an SDI output through configuration. In practical platforms, this reduces the need to maintain separate receive-only and transmit-only hardware variants, which can simplify both PCB planning and downstream qualification effort.

At the signal-chain level, the LMH0387 addresses the two dominant problems in coax-based SDI transport: frequency-dependent cable loss on the receive side and controlled high-integrity launch on the transmit side. The adaptive equalizer compensates for attenuation and dispersion introduced by long coax runs, especially at higher SDI rates where eye closure becomes the limiting factor before nominal amplitude does. This matters because SDI robustness is rarely determined by a single datasheet number; it depends on how well the receiver can recover timing margin after real cable-induced spectral tilt, connector discontinuities, and return-loss degradation. On the transmit side, the integrated cable driver provides a standards-oriented output stage suitable for direct coax interfacing, reducing the amount of external analog conditioning typically required around the port.

A notable implementation advantage is the integrated return-loss network. In many SDI designs, this network is a nontrivial source of layout sensitivity, BOM growth, and tuning iteration, particularly when multiple rates and cable lengths must be supported within the same product family. By absorbing this function into the device architecture, the LMH0387 helps stabilize port behavior across revisions and lowers the risk of analog mismatches between prototype intent and production execution. In dense broadcast or media-processing hardware, where several SDI channels may sit side by side, this level of analog integration often has a larger system impact than it first appears, because it improves repeatability across channels and reduces the number of small passive-value optimizations during bring-up.

Its standards coverage from SD-SDI through HD-SDI to 3G-SDI makes it suitable for equipment that must operate across mixed-generation infrastructures. That coverage is strategically useful in video systems because real deployments often remain heterogeneous for long periods. A device that can equalize and drive across the full SDI range supports smoother interoperability and delays forced redesign when product requirements expand from legacy transport into higher-bandwidth formats. When this is combined with long equalization reach on Belden 1694A cable, the part becomes especially relevant for edge cases where installation quality, patch-panel depth, or field cable length uncertainty would otherwise force conservative derating.

The SPI control interface is more than a convenience feature. It changes how the SDI port can be managed during validation and in deployed systems. Register-level access allows tuning, mode selection, and status-oriented control to be incorporated into firmware workflows, which is valuable when one hardware platform must support different operating profiles. During engineering characterization, this can shorten debug cycles because signal-path behavior can be adjusted without repeated hardware changes. In volume products, the same control path can support manufacturing test modes, board identification variants, or field configuration updates. In effect, SPI makes the analog front end partially software-defined, which is increasingly useful in modular equipment where physical ports are expected to serve multiple roles over the product life cycle.

From a sourcing perspective, the LMH0387 offers value beyond unit consolidation. When one component can cover input or output assignment, multiple SDI rates, and a substantial portion of the analog conditioning normally distributed across several design elements, the result is a narrower qualification matrix. That can reduce the operational burden associated with maintaining parallel approved parts for adjacent use cases. It also improves leverage in platform-based development, where a common mainboard may feed several products with only firmware, connector population, or enclosure-level differences. In such cases, the procurement benefit is not simply fewer line items, but lower change-management friction when forecasts shift across product variants.

Application fit is strongest in systems where port flexibility directly contributes to product value: digital video servers, modular broadcast frames, encoders, decoders, routing nodes, and distribution amplifiers. In these environments, the ability to repurpose a coax port through configuration supports denser function packing and more adaptable I/O definitions. That flexibility is especially useful in modular chassis designs, where one slot may need to behave differently depending on installed firmware or card personality. Designs built around fixed receive and fixed transmit devices often become constrained by panel mapping early in the product cycle. A configurable SDI front end delays that rigidity and gives more room for late-stage feature alignment.

In practical evaluation, the part should be reviewed with attention to board-level analog discipline rather than assuming integration alone guarantees margin. Equalization reach claims are meaningful only when connector launch quality, supply cleanliness, impedance control, and grounding strategy are aligned with high-speed coax practice. In lab work, the difference between acceptable and robust operation often appears first under marginal cable conditions, pathological source jitter, or repeated reclocking boundaries rather than in nominal short-cable tests. That is why the LMH0387 is most effective when treated as part of a full channel design, not as a drop-in fix for poor interconnect implementation. The integrated architecture reduces many common failure modes, but it does not remove the need to validate eye margin, pathological pattern handling, and interoperability across realistic cable and equipment combinations.

Viewed this way, the LMH0387 is best positioned as a platform-enabling SDI port device for designs that need flexibility, broad standards support, and controlled analog integration in a single component. Its real strength lies in shifting SDI port design from a collection of discrete receive/transmit choices toward a more unified and reusable interface strategy. For teams making engineering and sourcing decisions at the same time, that combination is often more valuable than any isolated electrical specification.