DS90LV001TM/NOPB >
DS90LV001TM/NOPB
Texas Instruments
IC REDRIVER LVDS 1CH 8SOIC
137656 Pcs New Original In Stock
Buffer, ReDriver 1 Channel 800Mbps 8-SOIC
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DS90LV001TM/NOPB Texas Instruments
5.0 / 5.0 - (100 Ratings)

DS90LV001TM/NOPB

Product Overview

1320928

DiGi Electronics Part Number

DS90LV001TM/NOPB-DG

Manufacturer

Texas Instruments
DS90LV001TM/NOPB

Description

IC REDRIVER LVDS 1CH 8SOIC

Inventory

137656 Pcs New Original In Stock
Buffer, ReDriver 1 Channel 800Mbps 8-SOIC
Quantity
Minimum 1

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In Stock (All prices are in USD)
  • QTY Target Price Total Price
  • 1 1.0999 1.0999
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DS90LV001TM/NOPB Technical Specifications

Category Interface, Signal Buffers, Repeaters, Splitters

Manufacturer Texas Instruments

Packaging Tube

Series -

Product Status Active

Type Buffer, ReDriver

Applications LVDS

Input CML, LVDS, LVPECL

Output LVDS

Data Rate (Max) 800Mbps

Number of Channels 1

Delay Time 1.4ns

Signal Conditioning -

Voltage - Supply 3V ~ 3.6V

Current - Supply 47mA

Operating Temperature -40°C ~ 85°C

Mounting Type Surface Mount

Package / Case 8-SOIC (0.154", 3.90mm Width)

Supplier Device Package 8-SOIC

Base Product Number DS90LV001

Datasheet & Documents

Manufacturer Product Page

DS90LV001TM/NOPB Specifications

HTML Datasheet

DS90LV001TM/NOPB-DG

Environmental & Export Classification

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 1 (Unlimited)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001

Additional Information

Other Names
-DS90LV001TM-NDR
*DS90LV001TM/NOPB
-DS90LV001TM/NOPB-DG
DS90LV001TMNOPB
DS90LV001TM-NDR
Standard Package
95

Alternative Parts

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SUBSTITUTE TYPE
FIN1101M
onsemi
939
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0.0110
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PI90LV03TEX
Diodes Incorporated
1046
PI90LV03TEX-DG
0.0110
MFR Recommended
DS90LV001TM
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5277
DS90LV001TM-DG
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Reviews

5.0/5.0-(Show up to 5 Ratings)
별빛이***는마당
de desembre 02, 2025
5.0
가격이 부담 없고, 직원분들이 정말 친절하세요. 강력 추천합니다.
Sunbe***ourney
de desembre 02, 2025
5.0
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de desembre 02, 2025
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I always find their prices to be fair, and the quality never varies.
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de desembre 02, 2025
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de desembre 02, 2025
5.0
Their cost-effective packaging solutions are both practical and environmentally conscious.
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de desembre 02, 2025
5.0
DiGi Electronics offers affordable prices that suit any budget, making tech accessible to everyone.
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de desembre 02, 2025
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Frequently Asked Questions (FAQ)

What are the key signal integrity risks when using the DS90LV001TM/NOPB to re-drive long LVDS traces on a 4-layer PCB, and how can I mitigate them?

The DS90LV001TM/NOPB is effective for restoring degraded LVDS signals, but improper PCB layout can negate its benefits. Key risks include impedance mismatches from uncontrolled differential pair routing, crosstalk from adjacent high-speed lines, and ground bounce due to inadequate return paths. To mitigate, maintain a consistent 100Ω differential impedance using a solid ground plane beneath the traces, keep the LVDS pair tightly coupled (≤5 mils spacing), and place decoupling capacitors (0.1µF + 10µF) within 2mm of the VCC pin. Avoid vias if possible; if needed, use symmetric via placement to preserve balance. These steps ensure the DS90LV001TM/NOPB operates within its 800 Mbps capability without introducing jitter or reflections.

Can the DS90LV001TM/NOPB safely replace a TI SN65LVDS1 in a legacy 3.3V LVDS link, and what design changes might be required?

Yes, the DS90LV001TM/NOPB can replace the SN65LVDS1 in most 3.3V LVDS applications, but with caveats. While both support 3.3V operation and LVDS I/O, the DS90LV001TM/NOPB is a redriver (not just a buffer), meaning it actively reshapes degraded signals—ideal for longer channels. However, the SN65LVDS1 has a lower propagation delay (~1.1 ns typical vs. 1.4 ns for DS90LV001TM/NOPB), which may affect timing margins in ultra-high-speed synchronous systems. Verify your setup/hold times and consider adding slight delay compensation in FPGA logic if needed. Also, confirm that your input signal type (CML, LVDS, or LVPECL) is compatible—DS90LV001TM/NOPB accepts all three, offering greater flexibility than the SN65LVDS1.

How does the DS90LV001TM/NOPB perform under thermal stress in an enclosed industrial enclosure with ambient temperatures reaching 75°C, and what derating should I apply?

The DS90LV001TM/NOPB is rated for -40°C to 85°C operation, so it will function at 75°C ambient. However, in enclosed environments with limited airflow, internal junction temperature can exceed safe limits due to self-heating (47 mA × 3.3 V ≈ 155 mW dissipation). Use a thermal pad or expose the SOIC package’s thermal slug (if present) to an internal copper pour connected to ground. Monitor case temperature and ensure it stays below 80°C. For long-term reliability, consider reducing data rate slightly under peak thermal conditions or adding minimal airflow. Unlike MSL-3 devices, the DS90LV001TM/NOPB’s MSL-1 rating means no special handling is needed during assembly, even in high-humidity factories.

What happens if I accidentally apply a 5V LVPECL signal to the input of the DS90LV001TM/NOPB, and how can I protect against overvoltage conditions?

Applying a 5V LVPECL signal directly to the DS90LV001TM/NOPB input will likely damage the device, as its absolute maximum input voltage is VCC + 0.3V (max ~3.9V with 3.6V supply). LVPECL typically swings from ~3.3V to ~4.2V, exceeding this limit. To safely interface 5V-tolerant LVPECL sources, use AC coupling with a series resistor (e.g., 50Ω) and a pull-down network to shift the common-mode voltage into the DS90LV001TM/NOPB’s acceptable range (0V to VCC – 0.4V). Alternatively, insert a level-shifting buffer like the MC100EP01 before the DS90LV001TM/NOPB. Always validate signal levels with an oscilloscope during prototyping to prevent latent failures.

Is the DS90LV001TM/NOPB suitable for daisy-chaining multiple redrivers in a multi-drop LVDS backbone, and what are the stability concerns?

Daisy-chaining multiple DS90LV001TM/NOPB devices is technically possible but introduces significant risk of signal degradation and instability. Each redriver adds ~1.4 ns delay and potential jitter accumulation, which can violate timing budgets in multi-gigabit links. More critically, improper termination or impedance discontinuities between stages may cause reflections that interact with the redrivers’ gain, leading to ringing or oscillation. If daisy-chaining is unavoidable, ensure each segment is properly terminated with 100Ω differential resistors at both ends, minimize stub lengths, and avoid exceeding two redrivers in series. For robust multi-drop systems, consider using a dedicated LVDS repeater hub or switching to a point-to-point topology instead of relying on cascaded DS90LV001TM/NOPB units.

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