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CDCM1804RGET
Texas Instruments
IC CLK BUFFER 1:3 800MHZ 24VQFN
1189 Pcs New Original In Stock
Clock Fanout Buffer (Distribution), Divider, Multiplexer IC 1:3 800 MHz 24-VFQFN Exposed Pad
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*Quantity
Minimum 1
Minimum 1
5.0 / 5.0
- (269 Ratings)
CDCM1804RGET
Product Overview
1253612
DiGi Electronics Part Number
CDCM1804RGET-DGManufacturer
Texas Instruments
CDCM1804RGET
Description
IC CLK BUFFER 1:3 800MHZ 24VQFNInventory
1189 Pcs New Original In Stock
Clock Fanout Buffer (Distribution), Divider, Multiplexer IC 1:3 800 MHz 24-VFQFN Exposed Pad
Quantity
Minimum 1
Minimum 1
Purchase and inquiry
Warranty & Returns
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CDCM1804RGET Technical Specifications
Category
Clock/Timing, Clock Buffers, Drivers
Packaging
Cut Tape (CT) & Digi-Reel®
Series
-
Product Status
Active
Type
Fanout Buffer (Distribution), Divider, Multiplexer
Number of Circuits
1
Ratio - Input:Output
1:3
Differential - Input:Output
Yes/Yes
Input
CML, HSTL, LVDS, LVPECL, LVTTL, SSTL-2, VML
Output
LVCMOS, LVPECL
Frequency - Max
800 MHz
Voltage - Supply
3V ~ 3.6V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-VFQFN Exposed Pad
Supplier Device Package
24-VQFN (4x4)
Base Product Number
CDCM1804
Datasheet & Documents
HTML Datasheet
CDCM1804RGET-DG
Environmental & Export Classification
RoHS Status
ROHS3 Compliant
Moisture Sensitivity Level (MSL)
2 (1 Year)
REACH Status
REACH Unaffected
ECCN
EAR99
HTSUS
8542.39.0001
Additional Information
Other Names
TEXTISCDCM1804RGET
296-18094-2
296-18094-1
2156-CDCM1804RGET
296-18094-1-NDR
-SN0305042RTHT-NDR
296-18094-6
-CDCM1804RGETG4-NDR
-296-18094-1-DG
-296-18094-1-NDR
-SN0305042RTHT
296-18094-2-NDR
-CDCM1804RGETG4
-296-18094-1
-CDCM1804RGET-NDR
Standard Package
250
Alternative Parts
PART NUMBER
MANUFACTURER
QUANTITY AVAILABLE
DiGi PART NUMBER
UNIT PRICE
SUBSTITUTE TYPE
Reviews
5.0/5.0-(Show up to 5 Ratings)
de desembre 02, 2025
디지 일렉트로닉스의 물류 시스템이 정말 체계적이고 믿음이 갑니다.
de desembre 02, 2025
저렴한 가격에 양질의 서비스를 제공해주셔서 감사하게 생각합니다.
de desembre 02, 2025
Je peux toujours compter sur leur rapidité d'expédition et leur soutien après-vente.
de desembre 02, 2025
素早い配送と明確な価格設定が、お客様の信頼を得る要因です。
de desembre 02, 2025
Their packaging quality is consistently top-notch, which reflects their attention to detail.
de desembre 02, 2025
Excellent customer support that truly cares and a shipping process that’s quick.
de desembre 02, 2025
I am satisfied with their prompt responses and the high quality of their offerings.
de desembre 02, 2025
Affordable and environment-friendly—supporting DiGi Electronics is a no-brainer.
de desembre 02, 2025
Responsive and helpful, their support team makes the entire experience smooth.
de desembre 02, 2025
Fast delivery times and supportive post-sales service make my experience enjoyable.
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Frequently Asked Questions (FAQ)
What are the key design-in risks when using the CDCM1804RGET in a mixed-signal PCB with high-speed ADCs and FPGAs?
When integrating the CDCM1804RGET in mixed-signal systems, a major risk is clock jitter accumulation due to power supply noise coupling into the sensitive clock distribution path. Since the CDCM1804RGET operates up to 800 MHz and supports LVPECL outputs, ensure a clean 3.3V supply with dedicated LDO regulation and proper grounding of the exposed pad to minimize jitter. Use separate ground planes for analog and digital sections, and route clock traces with controlled impedance and minimal stubs. Also, avoid sharing supply lines with switching regulators. The CDCM1804RGET's wide input compatibility (LVDS, HSTL, etc.) allows flexible sourcing, but always match termination schemes to the selected input standard to prevent reflections.
Can the CDCM1804RGET replace the CDCM1803RGER in a 1:3 LVPECL clock tree design, and what layout adjustments are needed?
Yes, the CDCM1804RGET can replace the CDCM1803RGER in a 1:3 LVPECL configuration, but with careful attention to output drive differences. The CDCM1804RGET supports both LVCMOS and LVPECL outputs, whereas the CDCM1803 is optimized for LVPECL-only. When replacing, verify output loading: LVCMOS outputs on the CDCM1804RGET may introduce higher skew if driving long PCB traces intended for LVPECL. To mitigate, use series termination and check propagation delay matching across outputs. Update your layout to accommodate the 24-VQFN (4x4) footprint alignment and ensure consistent trace lengths (<50 mils mismatch) to maintain skew performance. Also, confirm supply decoupling (0.1 µF + 1 µF) near VCC pins.
How does input signal integrity affect CDCM1804RGET jitter performance when using LVDS versus LVPECL clocks?
The CDCM1804RGET's jitter performance is highly dependent on input signal quality. LVPECL provides better noise margin and faster edge rates than LVDS at 800 MHz, but requires proper AC-coupling and 50Ω termination to VTT (typically VCC - 2V). LVDS inputs are less susceptible to ground shifts but more vulnerable to EMI on long traces. To minimize additive jitter from the CDCM1804RGET, maintain input rise/fall times under 100 ps and ensure input signals meet the required voltage swing specs (±350mV differential for LVDS, 600–1000mV for LVPECL). Use matched-length differential pairs and avoid sharp bends in routing. Poor input integrity can degrade the CDCM1804RGET’s output phase noise by up to 20%.
What are the thermal and reliability concerns when deploying the CDCM1804RGET in a densely populated 4-layer board at 85°C ambient?
At 85°C ambient temperature, thermal management is critical for the CDCM1804RGET in high-density layouts. The 24-VQFN (4x4) package has an exposed thermal pad that must be soldered to a solid copper ground plane using a thermal via array (6–9 via arrangement, 0.3mm drills) for efficient heat dissipation. Without proper thermal relief, junction temperature may exceed 125°C, risking long-term reliability and increased jitter. Also, the MSL 2 rating requires the CDCM1804RGET to be reflow-soldered within 1 year of dry pack opening or subjected to baking per J-STD-033. Avoid placing the CDCM1804RGET near high-power components and verify thermal performance with infrared testing during prototype.
Is the CDCM1804RGET a suitable pin-compatible upgrade from the Si53302-B-GMR in a high-frequency clock buffer application?
The CDCM1804RGET is not pin-compatible with the Silabs Si53302-B-GMR due to different package configurations (24-VQFN vs. 24-QFN) and power pin arrangements, but it can serve as a functional equivalent in 1:3 fanout applications up to 800 MHz. The CDCM1804RGET offers broader input flexibility (CML, HSTL, LVDS, etc.) compared to the Si53302’s fixed LVPECL input, allowing more integration options. However, unlike the Si53302, the CDCM1804RGET lacks integrated PLLs, so it cannot regenerate or clean jitter on the input clock. Use the CDCM1804RGET only when sourcing a low-jitter reference and update both footprint and power sequencing logic during replacement. Validate output skew and signal integrity on the redesigned board.
Quality Assurance (QC)
DiGi ensures the quality and authenticity of every electronic component through professional inspections and batch sampling, guaranteeing reliable sourcing, stable performance, and compliance with technical specifications, helping customers reduce supply chain risks and confidently use components in production.
CDCM1804RGET CAD Models
Texas Instruments CDCM1804RGET PCB symbols & footprints
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