CDCE913PW >
CDCE913PW
Texas Instruments
IC SS CLOCK DRIVER 14TSSOP
9874 Pcs New Original In Stock
Spread Spectrum Clock Driver IC 230MHz 1 14-TSSOP (0.173", 4.40mm Width)
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CDCE913PW Texas Instruments
5.0 / 5.0 - (476 Ratings)

CDCE913PW

Product Overview

1268371

DiGi Electronics Part Number

CDCE913PW-DG

Manufacturer

Texas Instruments
CDCE913PW

Description

IC SS CLOCK DRIVER 14TSSOP

Inventory

9874 Pcs New Original In Stock
Spread Spectrum Clock Driver IC 230MHz 1 14-TSSOP (0.173", 4.40mm Width)
Quantity
Minimum 1

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In Stock (All prices are in USD)
  • QTY Target Price Total Price
  • 1 7.4824 7.4824
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CDCE913PW Technical Specifications

Category Clock/Timing, Clock Generators, PLLs, Frequency Synthesizers

Manufacturer Texas Instruments

Packaging Tube

Series -

Product Status Active

DiGi-Electronics Programmable Verified

Type Spread Spectrum Clock Driver

PLL Yes with Bypass

Input LVCMOS, Crystal

Output LVCMOS

Number of Circuits 1

Ratio - Input:Output 1:3

Differential - Input:Output No/No

Frequency - Max 230MHz

Divider/Multiplier Yes/Yes

Voltage - Supply 1.7V ~ 1.9V, 2.3V ~ 3.6V

Operating Temperature -40°C ~ 85°C

Mounting Type Surface Mount

Package / Case 14-TSSOP (0.173", 4.40mm Width)

Supplier Device Package 14-TSSOP

Base Product Number CDCE913

Datasheet & Documents

HTML Datasheet

CDCE913PW-DG

Environmental & Export Classification

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 1 (Unlimited)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001

Additional Information

Other Names
-296-22670-5-DG
-CDCE913PW-NDR
-CDCE913PWG4-NDR
-CDCE913PWG4
296-22670-5-NDR
296-22670-5
-296-22670-5
-296-22670-5-NDR
Standard Package
90

Alternative Parts

PART NUMBER
MANUFACTURER
QUANTITY AVAILABLE
DiGi PART NUMBER
UNIT PRICE
SUBSTITUTE TYPE
CDCE913PWG4
Texas Instruments
939
CDCE913PWG4-DG
0.0748
MFR Recommended

Reviews

5.0/5.0-(Show up to 5 Ratings)
Zep***Zone
de desembre 02, 2025
5.0
They have a track record of delivering products on time, even during peak seasons.
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de desembre 02, 2025
5.0
Thanks to their timely support, we've experienced very few post-purchase concerns.
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de desembre 02, 2025
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Their price advantage is clear, and delivery is consistently punctual.
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de desembre 02, 2025
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Frequently Asked Questions (FAQ)

What are the key design-in considerations when using the CDCE913PW in a mixed-voltage system to avoid supply rail conflicts?

When integrating the CDCE913PW in mixed-voltage systems, ensure the dual supply ranges (1.7V–1.9V and 2.3V–3.6V) are properly segregated to avoid contention. The device uses separate VDDA and VDDB pins—VDDA must be within 1.7V–1.9V for internal PLL operation, while VDDB (2.3V–3.6V) powers outputs. Sequence supplies such that VDDA powers up before or simultaneously with VDDB to prevent latch-up. Use local ferrite beads and bypass capacitors (100nF ceramic + 1μF) near each supply pin to suppress noise coupling, especially when driving three LVCMOS outputs simultaneously at up to 230MHz.

Can the CDCE913PW reliably replace an Si5351A in a cost-sensitive timing application, and what are the critical trade-offs?

The CDCE913PW can replace the Si5351A in cost-sensitive designs requiring spread spectrum clocking, but with key limitations. Unlike the Si5351A, the CDCE913PW lacks I2C programmability and fixed 1:3 ratio output, reducing flexibility in frequency agility. However, it offers better EMI reduction via integrated spread spectrum and lower jitter in single-frequency applications. Use the CDCE913PW when fixed-ratio clock distribution with EMI control is prioritized over multi-rate flexibility. Validate output drive strength compatibility—CDCE913PW drives 15pF loads vs. Si5351A’s 10pF—especially over longer PCB traces.

How does the CDCE913PW handle crystal input stability, and what layout practices minimize timing errors in noisy environments?

The CDCE913PW relies on a stable crystal connected to the XI/XO pins, and poor layout can induce jitter or startup failures. Use a fundamental-mode, low-load capacitance (12–18pF) crystal with ESR <60Ω. Keep crystal traces short (<1 inch), symmetrical, and shielded from high-speed signals. Route ground planes underneath to minimize noise coupling. Include 10–22Ω series resistors near XI to damp oscillations and use 1–10pF parallel load capacitors referenced to clean analog ground. Avoid routing digital or switching signals beneath the crystal to preserve timing integrity.

What are the risks of exceeding the 230MHz maximum output frequency on the CDCE913PW, even briefly during startup or fault conditions?

Exceeding the 230MHz output limit—even transiently—can cause erratic LVCMOS switching, increased crosstalk, and potential violation of timing margins in downstream logic like FPGAs or ADCs. The CDCE913PW lacks over-frequency protection, so ensure input clock and PLL multiplier settings prevent out-of-spec output under all conditions, including crystal drift at temperature extremes. For systems with variable input clocks, implement external monitoring or limit input frequency range during power-up sequencing to avoid metastability in connected devices.

In what high-reliability applications should the CDCE913PW be avoided due to thermal or EMI sensitivity, and what alternatives exist?

Avoid the CDCE913PW in thermally constrained environments (>85°C ambient) or ultra-low jitter systems (e.g., RF sampling, 10Gbps+ serial links) due to its inherent spread-spectrum-induced jitter (~150ps typical). Although rated for -40°C to 85°C, sustained high-temperature operation degrades PLL stability. For industrial-grade applications needing tighter jitter, consider the LMK04832 or CDCM6208. Also, ensure spread spectrum is necessary—its EMI benefit may not outweigh timing penalties in synchronous, short-trace designs where a fixed-clock buffer like the CDCM1803 might be preferable.

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