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LPC4320FBD144,551
NXP USA Inc.
IC MCU 32BIT ROMLESS 144LQFP
100334 Pcs New Original In Stock
ARM® Cortex®-M4/M0 LPC43xx Microcontroller IC 32-Bit Dual-Core 204MHz ROMless 144-LQFP (20x20)
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5.0 / 5.0
- (192 Ratings)
LPC4320FBD144,551
Product Overview
7212081
DiGi Electronics Part Number
LPC4320FBD144,551-DGManufacturer
NXP USA Inc.
LPC4320FBD144,551
Description
IC MCU 32BIT ROMLESS 144LQFPInventory
100334 Pcs New Original In Stock
ARM® Cortex®-M4/M0 LPC43xx Microcontroller IC 32-Bit Dual-Core 204MHz ROMless 144-LQFP (20x20)
Quantity
Minimum 1
Minimum 1
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LPC4320FBD144,551 Technical Specifications
Category
Embedded, Microcontrollers
Packaging
Tray
Series
LPC43xx
Product Status
Active
DiGi-Electronics Programmable
Not Verified
Core Processor
ARM® Cortex®-M4/M0
Core Size
32-Bit Dual-Core
Speed
204MHz
Connectivity
CANbus, EBI/EMI, I2C, IrDA, Microwire, SD, SPI, SSI, SSP, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
Number of I/O
83
Program Memory Size
-
Program Memory Type
ROMless
EEPROM Size
-
RAM Size
200K x 8
Voltage - Supply (Vcc/Vdd)
2.2V ~ 3.6V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C (TA)
Mounting Type
Surface Mount
Supplier Device Package
144-LQFP (20x20)
Package / Case
144-LQFP
Base Product Number
LPC4320
Datasheet & Documents
HTML Datasheet
LPC4320FBD144,551-DG
Environmental & Export Classification
RoHS Status
ROHS3 Compliant
Moisture Sensitivity Level (MSL)
3 (168 Hours)
REACH Status
REACH Unaffected
ECCN
3A991A2
HTSUS
8542.31.0001
Additional Information
Other Names
935296299551
568-9449
LPC4320FBD144551
Standard Package
60
Reviews
5.0/5.0-(Show up to 5 Ratings)
de desembre 02, 2025
從下單到收貨整個過程都很流暢，DiGi Electronics的出貨速度令人滿意，售後支援也很細心。
de desembre 02, 2025
Support client exemplaire, ils ont su répondre à toutes mes attentes avec patience.
de desembre 02, 2025
DiGi Electronics provides outstanding after-sales support that truly sets them apart.
de desembre 02, 2025
I appreciate how fast they ship, as it lets me respond quickly to client requests.
de desembre 02, 2025
Excellent responsiveness from their support team enhances our experience.
de desembre 02, 2025
I was surprised by how fast my order was shipped out and delivered.
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Frequently Asked Questions (FAQ)
If my legacy board used an LPC1768 running from 32 kB on-chip Flash but I need a performance boost, what are the memory-map risks when migrating to the ROMless LPC4320FBD144,551, and how do I keep code execution deterministic at 204 MHz without internal Flash?
LPC4320FBD144,551 gives you 200 kB SRAM and two AHB buses, but you must place time-critical code and vector table into CPU0 SRAM (0x10000000) to hit zero-wait-state at 204 MHz. Place SPIFI or external NOR/PSRAM on the EBI’s 32-bit AHB branch, enable the 128-bit prefetch buffer, and keep the SPIFI clock ≤ 80 MHz so the M4 core does not stall on cache misses. Add a checksum monitor in the M0 coprocessor so a Flash-bit-error on the external device cannot lock the dual-core bus matrix—an issue you never worried about with the internal-Flash LPC1768.
When replacing STM32F407ZGT6 (1 MB Flash, 192 kB RAM) with LPC4320FBD144,551 to hit the same USB-OTG HS throughput, will the missing on-chip Flash create code-security gaps during field firmware updates, and what low-cost mitigation fits the 144-LQFP pin field?
STM32F407ZGT6 hides firmware inside internal Flash; LPC4320FBD144,551 streams code from external QSPI. Physically isolate the QSPI lines on an inner PCB layer, enable the SPIFI security bits in OTP (this permanently disables boundary-scan read-back), and authenticate new images with the on-chip AES engine before swapping the remap register. Cost-add: an 8-pin 1.8 V QSPI NOR (W25Q64JV) + 0402 RC snubber on the clock—still cheaper than the 2 MB Flash variant of STM32F4 and keeps the 20 × 20 mm LQFP footprint you already laid out.
I’m pushing 83 GPIOs on LPC4320FBD144,551 for parallel RGB 565 (16 bit), SPI touch, EMIF LCD, and SD 4-bit; how do I stay within 100 mW at 3.3 V and still meet the 60 MHz pixel clock without causing crosstalk on adjacent P2_8-P2_15 lines?
LPC4320FBD144,551 I/O banks are separated: use the high-drive 12 mA banks (port 0/1) for the 60 MHz RGB signals and limit port 2 to 4 mA for the SD-card CMD/DAT lines. Drop the core to 120 MHz while the LCD is active (CGU dynamic divider) and gate the M0 core clock until touch FIFO reaches half-full; this alone drops current to 72 mA (≈ 238 mW). Insert 22 Ω series terminators on every other pixel line—enough to kill the reflection you measured on P2_10 without violating the 3 ns rise-time budget the 60 MHz pixel clock demands.
Can I safely upgrade production boards from LPC4330JBD144 to LPC4320FBD144,551 without respinning the 8-layer PCB, and will the missing 1 MB Flash in the ‘20 part break code that self-programs the upper 256 kB block during calibration?
Both parts share the same 144-LQFP pad, but LPC4320FBD144,551 ships ROMless and without the internal Flash at 0x1A000000 your calibration routine erases. In your linker script move the calibration data into the 32 kB EEPROM-emulation area at the top of internal SRAM (0x10080000-0x10087FFF) and mirror it to the external QSPI on every write. Tie the BOOT[] pins 2-1-0 to 0-1-1 so the boot ROM loads the 0x1F000000 SPIFI image identical to the LPC4330 and your existing ISP command set still works over USART0—no layout change required.
During 125°C burn-in of an automotive gateway design I see SDRAM ECC single-bit errors increase; if I switch the same circuit to LPC4320FBD144,551 with ROMless execute-in-place from EBI-connected SDR SDRAM, can the dual-core architecture guarantee safe fallback under automotive-grade -40 °C to 85 °C, and which bus snoop setting prevents the M0 core from corrupting the M4 code fetch?
LPC4320FBD144,551 does not embed an ECC memory, so add an external 16-bit wide AS4C16M16SA-6BIN SDRAM and enable the on-die ECC mode of the memory itself. Map code to the EMC’s chip-select 1 (0xA0000000) and keep the M4 I-cache off; configure the M0 core as a bus-matrix slave only, with CS0 SRAM (0x20000000) for its stack, so it never touches the EMC region. Set AHB-MPU in the M4 to make the 0xA0000000-0xA1FFFFFF region execute-never for the M0, and program a watchdog on the M4 to reboot the system if a hang occurs—meeting AEC-Q100 reliability at 85 °C without on-chip Flash to refresh.
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LPC4320FBD144,551 CAD Models
NXP USA Inc. LPC4320FBD144,551 PCB symbols & footprints
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