Is SERDES the right choice for your required bandwidth, transmission distance, and system design? The answer depends on lane rate, protocol compatibility, signal integrity, power, and channel loss. This article explains how SERDES works, compares its main architectures and signaling methods, and provides practical guidance for selecting, validating, and troubleshooting a reliable high-speed link.
What Is SERDES?
SERDES stands for Serializer/Deserializer. It is a circuit or functional block that converts parallel data into a serial bitstream at the transmitter and converts the received serial bitstream back into parallel data at the receiver. The serializer accepts multiple bits simultaneously from a processor, FPGA fabric, ASIC, image sensor, or communication controller and transmits them sequentially through one serial lane or several bonded lanes. At the receiving end, the deserializer reconstructs the original bit order and presents the data to the receiving digital logic in parallel form.
SERDES is not a complete communication protocol but rather a data-conversion and physical-transmission function used in interfaces such as PCI Express, Ethernet, SATA, SAS, USB, DisplayPort, MIPI, automotive video links, and proprietary FPGA-to-FPGA connections. Modern SERDES implementations may also include features such as data encoding or scrambling, transmit clock generation, differential line driving, clock and data recovery, transmitter and receiver equalization, bit, word, and lane alignment, link training, loopback and diagnostic functions, and error detection or forward error correction.
How SERDES Works
SERDES transfers parallel data over a high-speed serial link by converting multiple input bits into a single serial stream and reconstructing them at the receiving end. Before transmission, the data may be encoded or scrambled to improve signal integrity and support reliable clock recovery. The serializer then sends the data through a differential channel, such as a PCB trace, cable, or backplane, using high-speed transmit drivers. At the receiver, the input buffer and equalizer compensate for signal loss, while the clock and data recovery (CDR) circuit extracts timing directly from the incoming data. The deserializer restores the original parallel data, and the decoder or descrambler reconstructs the final output for the receiving digital system.
Common SERDES Link Configurations
SERDES links can be classified by clocking method, data encoding, and lane organization. These features are not mutually exclusive and may be combined within the same interface.
Parallel-Clock SERDES
A parallel-clock, or source-synchronous, SERDES transmits a separate clock signal alongside the serialized data. The receiver uses this forwarded clock to sample the incoming data instead of recovering timing from the data stream itself. This approach simplifies receiver design but requires the clock and data signals to remain closely matched to minimize timing skew.
Embedded-Clock SERDES
An embedded-clock SERDES does not use a separate clock signal. Instead, timing information is embedded within the serial data stream and recovered by the receiver through a Clock and Data Recovery (CDR) circuit. Data encoding or scrambling is typically used to provide enough signal transitions for reliable clock recovery.
Encoded SERDES
An encoded SERDES applies a coding scheme to the data before serialization to improve transmission reliability. Encoding helps maintain transition density, DC balance, control characters, block boundaries, error detection, and lane-alignment markers. Common encoding methods include 8b/10b and 64b/66b, although encoding introduces protocol overhead. For example, 8b/10b encoding transmits 10 line bits for every 8 bits of payload data.
Interleaved and Multi-Lane SERDES
An interleaved or multi-lane SERDES distributes data across multiple high-speed serial lanes to increase total bandwidth. The receiver combines the data streams by performing lane identification, lane ordering, deskew, and channel bonding to reconstruct the original data correctly. Multi-lane architectures support much higher data rates than a single lane but require additional transceiver resources, PCB routing, pins, and power.
NRZ vs. PAM4 Signaling
NRZ Signaling
Non-return-to-zero, or NRZ, uses two signal levels. One level represents binary 0, while the other represents binary 1.
Each symbol carries one bit:
Bit rate = Symbol rate
NRZ produces one eye opening and provides wider voltage separation between its two levels than a four-level system using the same total signal swing.
PAM4 Signaling
Four-level pulse-amplitude modulation, or PAM4, uses four voltage levels. Each symbol represents two bits:
• 00
• 01
• 10
• 11
Because each symbol carries two bits, PAM4 can transfer twice the bit rate of NRZ at the same symbol rate.
For example:
• 25 GBd NRZ carries 25 Gb/s
• 25 GBd PAM4 carries 50 Gb/s before coding overhead
PAM4 produces three eye openings. Its smaller separation between adjacent levels makes it more sensitive to noise, jitter, distortion, crosstalk, and transmitter nonlinearity.
NRZ vs. PAM4 Comparison
| Parameter | NRZ | PAM4 |
|---|---|---|
| Signal Levels | Two | Four |
| Bits per Symbol | One | Two |
| Eye Openings | One | Three |
| Symbol Rate for Equal Bit Rate | Greater | Reduced |
| Voltage Separation | Wider | Narrower |
| Receiver Thresholds | One | Three |
| Noise Sensitivity | Less sensitive for equal signal swing | More sensitive |
| Equalization Requirement | Depends on rate and channel | Usually more demanding |
| Forward Error Correction | Protocol-dependent | Frequently used |
| Typical Use | Established serial interfaces | Bandwidth-dense networking and data-center links |
PAM4 is suitable when the required bit rate cannot be reached efficiently with NRZ, but it requires sufficient signal-to-noise ratio and more complex receiver processing.
Key SERDES Specifications
Lane Rate and Lane Count
Lane rate is the transfer rate of one serial lane. It may be expressed in bits per second, transfers per second, symbols per second, or baud.
Common lane configurations include:
• x1
• x2
• x4
• x8
• x16
Additional lanes increase aggregate bandwidth but also require more pins, transceiver blocks, PCB traces, power, and alignment logic.
Raw and Payload Bandwidth
For identical lanes:
Aggregate Raw Bandwidth = Lane Bit Rate × Number of Lanes
Four lanes operating at 10 Gb/s provide 40 Gb/s of raw bandwidth. Usable payload bandwidth is lower because the link also carries encoding, headers, control symbols, idle sequences, training data, and forward error correction.
For modulation-based calculations:
Raw Bit Rate = Symbol Rate × Bits per Symbol × Number of Lanes
NRZ carries one bit per symbol, while PAM4 carries two bits per symbol.
Serialization Ratio
The serialization ratio indicates how many parallel bits are converted into a serial stream during each internal data cycle. Common serialization ratios range from 4:1 to 40:1, depending on the transceiver architecture, internal datapath width, fabric clock, latency, and protocol requirements.
Reference Clock and Jitter
The reference clock must meet the transceiver requirements for frequency, tolerance, phase noise, jitter, duty cycle, and multiplication range. A clock may have the correct nominal frequency but still cause CDR instability or bit errors when its phase noise or jitter exceeds the permitted limit.
Bit-Error Rate
Bit-error rate, or BER, is calculated as:
BER = Incorrectly Received Bits ÷ Total Transmitted Bits
A BER of 10⁻¹² represents an average of one incorrect bit per trillion transmitted bits. The acceptable BER depends on the protocol, application, and error-correction method.
Channel Loss and Reach
The channel-loss budget must include IC packages, PCB traces, vias, connectors, backplanes, cables, and test fixtures. Transmission distance alone does not determine link quality. A short channel with several impedance discontinuities may perform worse than a longer, well-controlled channel made with lower-loss materials.
Latency, Power, and Thermal Requirements
SERDES latency may include encoding, serialization, physical propagation, deserialization, lane deskew, elastic buffering, error correction, and protocol processing. Power consumption depends on lane rate, lane count, modulation, equalization, output swing, PLL activity, and protocol logic. These requirements must remain within the device, package, and system thermal limits.
How to Select a SERDES Solution
Calculate Payload Bandwidth
Begin by determining the required payload bandwidth based on the application's average throughput, peak throughput, read and write requirements, burst duration, simultaneous traffic, protocol overhead, and expected future expansion. Size the SERDES link using peak bandwidth rather than average traffic to ensure reliable performance under maximum load.
Choose the Protocol
Select a communication protocol based on system requirements. Standard protocols such as PCIe or Ethernet are suitable when devices from different vendors must interoperate, while proprietary SERDES links are often used between custom FPGA or ASIC designs where framing, synchronization, and error handling are fully controlled.
Select Lane Rate and Lane Count
Choose an appropriate combination of lane rate and lane count to achieve the required bandwidth. Fewer high-speed lanes reduce pin count but demand better PCB materials, stronger equalization, and lower clock jitter, while more lanes lower the speed per lane at the cost of additional transceivers, routing, and power.
Define the Physical Channel
Define the complete transmission path, including PCB length and material, layer structure, vias, connectors, cables, backplanes, and operating temperature. The entire channel must remain within the allowable signal-loss budget for reliable communication.
Check Equalization and Clock Requirements
Verify that the SERDES supports the required equalization features, such as output-swing adjustment, pre-emphasis, de-emphasis, feed-forward equalization, CTLE, DFE, adaptive equalization, and link training. Also confirm that the reference clock meets the required frequency, accuracy, multiplication range, and jitter specifications.
Review Latency, Power, and Device Resources
Ensure the selected FPGA or ASIC provides sufficient transceiver lanes, PLL resources, reference-clock inputs, protocol IP, fabric performance, and supported lane rates. Power consumption, thermal limits, package type, speed grade, and development tool requirements should also be evaluated.
Plan Validation
Prepare a validation plan that verifies link performance through eye-mask testing, BER measurement, jitter analysis, receiver tolerance testing, channel-loss measurement, protocol compliance, interoperability testing, and operation across voltage and temperature ranges.
SERDES Performance and Equalization
Channel Loss and Inter-Symbol Interference
Copper channels attenuate higher-frequency signal components, slowing signal edges and reducing the eye opening. Inter-symbol interference may result from PCB dielectric and conductor losses, reflections, via stubs, connector discontinuities, cable attenuation, and limited channel bandwidth.
Jitter and Clock Quality
Jitter can come from reference-clock phase noise, PLL noise, power-supply ripple, crosstalk, duty-cycle distortion, data-dependent interference, and periodic switching noise. Excessive jitter reduces the receiver's horizontal sampling margin and increases the risk of bit errors.
Crosstalk and Power-Supply Noise
Crosstalk may originate from nearby SERDES pairs, memory buses, clock traces, switching regulators, oscillators, high-current paths, and connector pins. Power-supply noise can also disturb the PLL, CDR, transmitter, and receiver, so sensitive transceiver rails may require dedicated filtering.
Temperature and Voltage Variation
Temperature and supply-voltage changes can affect transmitter amplitude, receiver gain, equalizer response, PLL operation, CDR locking margin, channel loss, and semiconductor timing. The complete SERDES link should therefore be tested across its specified voltage and temperature range.
Transmitter Equalization
Transmitter equalization uses pre-emphasis, de-emphasis, or feed-forward equalization to compensate for expected channel loss. An FFE adjusts precursor, main-cursor, and postcursor taps to shape the transmitted signal.
Receiver Equalization
Receiver equalization may use CTLE, DFE, variable-gain amplification, and adaptive threshold control. CTLE compensates for frequency-dependent channel loss, while DFE reduces postcursor interference using previous symbol decisions.
SERDES Protocols and Applications
| Application | Common Interface | Practical Use |
|---|---|---|
| Computer Expansion | PCI Express | GPUs, SSDs, accelerators, network cards, and FPGA boards |
| Processor and Memory Connectivity | CXL over PCIe physical infrastructure | Memory expansion, accelerators, and coherent devices |
| Networking | Ethernet | Switches, routers, servers, optical modules, and network adapters |
| Storage | SATA and SAS | Drives, storage controllers, and storage arrays |
| External Connectivity | USB and Thunderbolt | Peripheral devices, docking stations, and external storage |
| Displays | DisplayPort and HDMI implementations | Monitors, embedded displays, and video systems |
| Mobile Cameras and Displays | MIPI CSI-2 and DSI | Camera-to-processor and processor-to-display links |
| FPGA Communication | Aurora and proprietary protocols | FPGA-to-FPGA and board-to-board data transfer |
| Automotive Systems | FPD-Link and related interfaces | Cameras, radar, displays, and driver-assistance systems |
| Industrial Imaging | Camera and proprietary links | Machine vision and inspection equipment |
| Telecommunications | Ethernet, Fibre Channel, and optical interfaces | Base stations, routers, backplanes, and optical transport |
| Data Centers and AI Systems | PCIe, CXL, and Ethernet | CPUs, GPUs, AI accelerators, switches, and optical DSPs |
A compatible line rate does not guarantee communication. Both devices must support the same electrical interface, modulation, encoding, training method, lane organization, and protocol.
How SERDES Relates to Other Interfaces and Circuits
SERDES is a serialization and deserialization function rather than a complete communication protocol or electrical interface. It may operate inside a larger transceiver or protocol PHY, while technologies such as LVDS define electrical signaling and parallel interfaces provide a different data-transfer architecture.
| Technology | Primary Function | Relationship to SERDES | Typical Use |
|---|---|---|---|
| SERDES | Converts parallel data into serial data and reconstructs it at the receiver | Provides the core serialization and deserialization function | High-speed chip-to-chip, board-to-board, cable, and backplane links |
| Parallel Interface | Transfers several data bits simultaneously over separate traces | An alternative architecture that avoids serialization but requires more pins and tighter skew control | Short board-level connections with moderate data rates |
| LVDS | Defines low-voltage differential electrical signaling | Can carry serialized or source-synchronous data, but does not define framing, encoding, or protocol behavior | Displays, converters, imaging systems, and short differential links |
| Ethernet PHY | Implements the Ethernet physical layer, including encoding, training, clock recovery, and media-specific transmission | May contain SERDES blocks as part of its PCS, PMA, or transceiver architecture | Standards-based networking over copper, backplanes, or optical media |
| Complete High-Speed Transceiver | Provides the complete transmit and receive signal chain | Usually includes SERDES, PLLs, CDR, line drivers, receivers, equalization, alignment, and test functions | FPGA, ASIC, networking, storage, and high-speed processor interfaces |
Common SERDES Problems and Solutions
| Problem | Solution | How to Fit |
|---|---|---|
| Link does not establish | Verify the reference clock and transceiver configuration. | Measure clock frequency, amplitude, and jitter, then confirm that the selected protocol and lane settings match both devices. |
| CDR does not lock | Correct the lane rate, signal amplitude, or transition density. | Check the configured transceiver rate, encoding method, input swing, and whether the data stream contains enough transitions for clock recovery. |
| Link operates only at a reduced rate | Reduce channel loss or improve equalization. | Review PCB traces, vias, connectors, cables, and equalizer settings against the supported loss budget. |
| Link fails intermittently | Improve timing, voltage, and signal margin. | Run eye, BER, temperature, and voltage-corner tests to identify the condition that causes the failure. |
| BER increases with cable length | Use a channel with lower attenuation or better impedance control. | Compare the cable and complete channel loss with the receiver limit and adjust equalization when supported. |
| BER increases at elevated temperature | Increase thermal and electrical operating margin. | Test the transmitter, receiver, PLL, and full channel across the specified temperature range. |
| One lane fails | Correct lane-specific mapping, polarity, or routing loss. | Test each lane separately and compare its eye opening, BER, polarity, and physical path with the working lanes. |
| Receiver cannot align data | Correct the encoding, alignment markers, or polarity settings. | Verify the encoder and decoder configuration, block boundaries, alignment characters, and polarity correction. |
| Data appears in the wrong order | Correct the lane mapping and deskew settings. | Check lane numbering, bonding order, and receiver deskew configuration on both ends of the link. |
| Eye has limited vertical opening | Reduce noise and compensate for attenuation. | Check supply filtering, transmitter output swing, receiver CTLE, and transmitter FFE settings. |
| Eye has limited horizontal opening | Reduce jitter, inter-symbol interference, and reflections. | Verify reference-clock quality, differential impedance, termination, channel loss, and discontinuities. |
| EMI test fails | Improve differential-pair symmetry and return paths. | Review trace matching, reference planes, connector grounding, via transitions, and pair separation from noise sources. |
| Transceiver repeatedly resets | Stabilize the PLL, CDR, clock, and reset sequence. | Check reset timing, lock indicators, reference-clock quality, supply stability, and firmware recovery behavior. |
| Link fails after a PCB revision | Recheck the updated stack-up and interconnect geometry. | Compare impedance, dielectric material, trace loss, via geometry, connectors, and routing transitions with the previous revision. |
| Simulation passes but hardware fails | Expand the channel model and manufacturing assumptions. | Include IC packages, connectors, cables, vias, tolerances, temperature effects, and process variation in the simulation model. |
Conclusion
A SERDES link is suitable when a design requires high aggregate bandwidth with fewer physical connections across PCB traces, connectors, cables, or backplanes. Select the solution by calculating payload bandwidth first, then confirming the protocol, lane rate, lane count, channel-loss budget, clock quality, equalization, power, and latency requirements. Use NRZ when it can meet the target rate with sufficient margin; choose PAM4 only when greater bandwidth density justifies its tighter signal-integrity and validation requirements. Finalize the design only after eye, jitter, BER, voltage, temperature, and interoperability testing confirm stable operation.
Frequently Asked Questions [FAQ]
Q1. Is SERDES a Communication Protocol?
No. SERDES is a data-conversion and physical-link function. Protocols such as PCIe and Ethernet use SERDES together with framing, training, flow control, and error-management functions.
Q2. What Is the Difference Between Bit Rate and Baud Rate?
Bit rate measures the number of bits transferred per second, while baud rate measures the number of symbols transmitted per second. NRZ carries one bit per symbol, whereas PAM4 carries two bits per symbol.
Q3. Why Does SERDES Need Clock and Data Recovery?
Clock and Data Recovery allows the receiver to determine the correct sampling time without a separate clock signal. It extracts timing information from transitions in the incoming serial data.
Q4. How Many SERDES Lanes Are Required?
Calculate the required payload bandwidth, include protocol overhead and operating margin, and divide the result by the usable bandwidth of one lane. The selected lane count must also match the supported protocol configuration.
Q5. What Determines the Maximum Transmission Distance?
Maximum distance depends on lane rate, modulation, PCB or cable loss, connector count, transmitter strength, receiver sensitivity, equalization, jitter, crosstalk, and the required BER.
Q6. Is PAM4 Always Better Than NRZ?
No. PAM4 carries two bits per symbol, but its four voltage levels reduce noise margin and increase transmitter, receiver, equalization, and testing requirements. NRZ may be more practical when two-level signaling can meet the required bandwidth.
