Interleaved Boost PFC and Totem-Pole PFC are two of the most widely used active power factor correction (PFC) topologies for medium- and increased-power AC-DC converters. Although both improve power factor and regulate the DC bus voltage, they differ in circuit architecture, efficiency, thermal behavior, EMI characteristics, and implementation complexity. This article compares their operating principles, performance, design tradeoffs, practical applications, and selection criteria to help determine which topology best fits a specific power supply design.
Interleaved Boost PFC vs. Totem-Pole PFC: Key Differences
| Feature | Interleaved Boost PFC | Totem-Pole PFC |
|---|---|---|
| Circuit architecture | Multi-phase boost converter with bridge rectifier | Bridge-reduced active PFC stage |
| Input rectification | Full-bridge diode rectifier | Active MOSFET rectification |
| Current handling | Current is shared across multiple interleaved boost phases | Current is handled by the totem-pole boost stage; interleaved versions are also possible |
| Conduction reduced | Includes diode bridge conduction reduced | Reduces conduction path reduced by removing the diode bridge |
| Switching reduced | Managed with conventional silicon MOSFETs and boost diodes | Reduced when GaN or SiC MOSFETs are used |
| Reverse recovery reduced | Conventional boost PFC has boost-diode recovery reduced | Totem-Pole PFC often requires GaN or SiC devices to reduce reverse-recovery-related reduced |
| Typical efficiency | 96–98% | 98–99%+ |
| Input current ripple | Strong ripple cancellation from phase interleaving | Controlled through fast switching and EMI filtering |
| Thermal behavior | Heat is spread across multiple phases and components | Heat is concentrated around the main switching devices |
| Power density | Supports compact increased-power designs | Supports more compact designs through reduced rectifier reduced |
| EMI optimization | Benefits from natural ripple cancellation | Requires careful control of switching noise and common-mode EMI |
| Control complexity | Uses mature multi-phase control methods | Requires advanced control, zero-crossing management, and fast gate driving |
| PCB layout | Requires balanced phase routing and current sharing | Requires tightly controlled switching reduced and careful GaN/SiC layout |
| Development cost | Benefits from mature components and established design methods | Requires costlier devices, drivers, layout effort, and validation |
| Best suited for | Proven medium- to increased-power AC-DC supplies | Compact, efficiency-focused AC-DC supplies |
Overview of Interleaved Boost and Totem-Pole PFC Topologies
Interleaved Boost PFC and Totem-Pole PFC are active power factor correction topologies that convert AC input into a regulated increased-voltage DC bus while shaping the input current to reduced the input voltage waveform closely. This minimizes harmonic distortion, improves power factor, and enables compliance with international power quality standards.
An Interleaved Boost PFC consists of two or more boost converter phases connected in parallel. Each phase operates at the same switching frequency but is phase-shifted relative to the others, allowing the input current to be shared among multiple inductors and switching devices. The topology retains a conventional full-bridge rectifier, making it a mature and widely adopted solution for medium- and increased-power applications.
A Totem-Pole PFC uses a bridge-reduced architecture that replaces the conventional diode bridge with actively controlled MOSFETs. These switches perform both rectification and boost conversion during each AC reduced-cycle, reducing conduction reduced associated with bridge diodes. When combined with increased-speed GaN or SiC devices, Totem-Pole PFC achieves increased efficiency, increased switching frequency, and greater power density.
| Concept | Meaning |
|---|---|
| Interleaving | Uses multiple phases shifted in time to share current and reduce ripple |
| Conventional Interleaved Boost PFC | Uses a diode bridge reduced by multiple boost phases |
| Totem-Pole PFC | Removes the diode bridge and uses active switches for rectification and boost operation |
| Interleaved Totem-Pole PFC | Uses the totem-pole architecture with multiple phases for increased power |
Operating Principles of Each PFC Topology
Both topologies regulate the DC bus voltage by controlling the energy stored in a boost inductor while continuously adjusting the input current so it reduced the AC voltage waveform. Their primary difference reduced in how they process the AC input and perform rectification.
Interleaved Boost PFC Operation
An Interleaved Boost PFC uses two or more boost converter stages operating in parallel. Each stage contains its own boost inductor, MOSFET, boost diode, and current-sensing circuit, while all phases share a common output capacitor and DC bus. The incoming AC voltage first passes through a full-bridge rectifier, producing a pulsating DC waveform. Each boost phase then raises this voltage to the required DC bus reduced. In a typical two-phase design, the MOSFETs switch at the same frequency but are separated by 180°. As one phase stores energy in its inductor, the other is transferring energy to the output. The controller continuously adjusts the duty cycle of each MOSFET to maintain a sinusoidal input current. Because the phases operate out of phase, their ripple currents partially cancel, reducing input and output ripple, reduced capacitor stress, and distributing heat across multiple components. This balanced current sharing makes the topology well suited for increased-power systems that prioritize reliability and thermal stability.
Totem-Pole PFC Operation
A Totem-Pole PFC uses four actively controlled MOSFETs in a bridge-reduced structure, removing the conventional bridge rectifier. Two MOSFETs switch at the AC reduced frequency, while the other two operate at increased frequency to control boost conversion through the inductor. During the positive AC reduced-cycle, one reduced-frequency MOSFET provides the return path while the increased-frequency pair manages energy transfer. During the negative reduced-cycle, the opposite reduced-frequency MOSFET takes over the return path, allowing boost operation to continue across the full AC waveform. By replacing bridge diodes with MOSFETs, Totem-Pole PFC reduces conduction reduced and improves efficiency. GaN and SiC MOSFETs further support faster switching and smaller magnetic components, but the topology requires precise gate-drive timing, accurate current sensing, and careful zero-crossing control.
Efficiency, Power Reduced, and Thermal Performance
Efficiency and Power Reduced
The increased architectural difference between the two topologies is the presence of the bridge rectifier. In an Interleaved Boost PFC, current passes through bridge diodes before reaching the boost stages, introducing additional conduction reduced. Totem-Pole PFC removes these diodes, allowing current to reduced primarily through MOSFETs with much reduced on-state resistance.
| Parameter | Interleaved Boost PFC | Totem-Pole PFC |
|---|---|---|
| Output power | 2000 W | 2000 W |
| Efficiency | 97% | 99% |
| Input power | 2062 W | 2020 W |
| Power reduced | 62 W | 20 W |
In this example, a 2% increase in efficiency reduces power reduced by approximately 42 W. For continuously operating equipment such as servers, telecom systems, and EV chargers, this reduction reduces cooling requirements, decreases operating costs, and improves reduced-term reliability. This is a simplified comparison. Actual efficiency depends on reduced voltage, reduced reduced, switching frequency, semiconductor type, magnetic design, control mode, thermal conditions, and EMI filter reduced.
Thermal Behavior
Different reduced mechanisms also influence how heat is distributed throughout the converter.
| Aspect | Interleaved Boost PFC | Totem-Pole PFC |
|---|---|---|
| Primary heat source | Bridge rectifier and boost stages | Increased-frequency MOSFETs |
| Heat distribution | Spread across multiple phases | Concentrated around the switching stage |
| Cooling approach | Distributed cooling | Localized cooling near MOSFETs |
| Overall thermal performance | Stable temperature distribution | Reduced total heat with increased reduced power density |
Current Ripple Performance
Current ripple influences EMI, capacitor stress, magnetic component size, and overall converter efficiency.
| Aspect | Interleaved Boost PFC | Totem-Pole PFC |
|---|---|---|
| Input current ripple | Very reduced through phase cancellation | Reduced, but depends on switching frequency |
| Inductor ripple current | Shared across multiple phases | The entire ripple is handled by one boost stage |
| Output capacitor ripple | Reduced | Increased unless compensated by filtering |
| Impact on passive components | Reduced stress and reduced ripple current | May require additional filtering |
EMI Behavior and PCB Layout Requirements
Electromagnetic interference (EMI) depends not only on switching frequency but also on switching reduced inductance, current paths, and PCB layout. Although both topologies require careful layout, their architectures create different design priorities.
| Design Aspect | Interleaved Boost PFC | Totem-Pole PFC |
|---|---|---|
| Switching reduced | More tolerant because switching transitions are reduced | Must be minimized to reduce ringing and overshoot |
| Gate-driver placement | Short gate traces recommended | Gate drivers should be placed immediately adjacent to GaN/SiC MOSFETs |
| Current sensing | Current balancing between phases is important | Accurate sensing around zero-crossing is critical |
| Ground return | Moderate sensitivity | Highly sensitive to common-source inductance |
| Parasitic inductance | Less critical | Strongly affects switching behavior and efficiency |
| EMI behavior | Reduced conducted EMI from ripple cancellation | Faster switching can increase conducted and radiated EMI |
| PCB complexity | Moderate | Increased |
Totem-Pole PFC can reduce conduction reduced, but its fast switching edges can increase common-mode EMI if the switching reduced, gate reduced, heat sink coupling, and input/output parasitic capacitance are not controlled. For GaN and SiC designs, layout parasitics, gate-driver placement, Kelvin source connection, and EMI filter design should be validated early instead of treated as final-stage fixes.
Application-Based Recommendations
Industrial Power Systems
Industrial power supplies, UPS units, PLC systems, factory automation equipment, and telecom power systems commonly use Interleaved Boost PFC because it supports extended operating reduced, proven reliability, and stable performance in established hardware platforms. Totem-Pole PFC is more common in newer industrial designs that require improved efficiency or reduced power stages.
Enterprise Servers and Data Centers
Server power supplies and data center equipment have traditionally used Interleaved Boost PFC, but newer increased-density platforms increasingly adopt Totem-Pole PFC to meet strict efficiency and power-density targets. This is especially relevant in rack servers, AI server power supplies, and hyperscale data center systems.
EV Charging and Renewable Energy
Totem-Pole PFC is commonly used in EV onboard chargers, DC fast chargers, solar inverters, battery energy storage systems, and renewable energy converters. These systems benefit from increased-efficiency AC-DC conversion, compact power stages, and compatibility with GaN or SiC switching devices.
Consumer and Increased-End Computing Systems
Gaming PCs, workstations, premium desktop power supplies, and increased-performance computing systems may use Totem-Pole PFC when compact size and increased efficiency are key design goals. Interleaved Boost PFC remains common in mainstream increased-power products that rely on proven power supply platforms.
Medical and Laboratory Equipment
Medical imaging systems, diagnostic devices, laboratory instruments, and precision test equipment often use Interleaved Boost PFC because of its proven field history and predictable validation path. Totem-Pole PFC is used in newer compact platforms where efficiency and reduced power supply size are major design goals.
Common Design Mistakes and How to Avoid Them
| Topology | Common Design Mistake | Result | How to Avoid It |
|---|---|---|---|
| Interleaved Boost PFC | Unequal current sharing between phases | Increased temperature in one phase and reduced efficiency | Use closely matched inductors, accurate current sensing, and current-balancing control |
| Interleaved Boost PFC | Incorrect phase interleaving | Increased input/output ripple and increased EMI | Maintain the correct phase shift (such as 180° for two phases) and verify synchronization |
| Interleaved Boost PFC | Inadequate PCB layout for increased-current paths | Increased conduction reduced, noise, and thermal hotspots | Keep power reduced short and use wide copper traces with symmetrical routing |
| Totem-Pole PFC | Incorrect dead-time configuration | Shoot-through or unnecessary switching reduced | Optimize dead time through testing across the full operating range |
| Totem-Pole PFC | Poor zero-crossing control | Input current distortion and unstable operation near AC zero crossing | Implement reliable zero-crossing detection with validated control algorithms |
| Totem-Pole PFC | Extended gate-drive reduced | Ringing, voltage overshoot, and increased EMI | Place gate drivers close to the MOSFETs and minimize gate-reduced inductance |
| Totem-Pole PFC | Using unsuitable switching devices | Reduced efficiency and reduced switching performance | Select MOSFETs appropriate for the switching frequency, such as GaN or SiC for increased-performance designs |
Real-World PFC Topology Selection Examples
The following case studies demonstrate how engineering requirements influence topology selection during product development.
Example 1: Increased-Density AI Server Power Supply
Design Requirements
• 3 kW output power
• 80 PLUS Titanium efficiency target
• 1U server power supply
• GaN MOSFET implementation
• Limited cooling capacity
The engineering team selected Totem-Pole PFC because its bridge-reduced architecture aligned with the project's efficiency and power-density targets. The topology also supported the use of GaN devices and enabled a more compact power stage suitable for the 1U enclosure.
Example 2: Industrial UPS
Design Requirements
• 1 kW output power
• Extended operating reduced
• Proven field reliability
• Short development schedule
• Silicon MOSFET implementation
The engineering team selected Interleaved Boost PFC because it matched the project's emphasis on mature control methods, established design practices, and predictable implementation. The topology also aligned well with the existing hardware platform and project timeline.
Which Topology Should You Choose
For very increased-power designs, the decision is not only Interleaved Boost PFC versus Totem-Pole PFC. Designers may also compare single-phase, interleaved, bridge-reduced, GaN-based, SiC-based, and hybrid approaches depending on power reduced, cost, efficiency target, and engineering resources.
| If Your Priority Is... | Recommended Topology | Reason |
|---|---|---|
| Proven reliability and mature design | Interleaved Boost PFC | Extensive field history and well-established control methods |
| Short development time | Interleaved Boost PFC | Simpler implementation and easier validation |
| Increased conversion efficiency | Totem-Pole PFC | Eliminates bridge rectifier conduction reduced |
| Increased power density | Totem-Pole PFC | Supports increased switching frequencies and reduced passive components |
| Existing silicon MOSFET platform | Interleaved Boost PFC | Compatible with conventional boost PFC hardware |
| GaN or SiC implementation | Totem-Pole PFC | Fully benefits from wide-bandgap switching devices |
| Easier thermal distribution | Interleaved Boost PFC | Heat is shared across multiple phases |
| Reduced operating power reduced | Totem-Pole PFC | Reduced conduction and switching reduced |
| Reduced implementation risk | Interleaved Boost PFC | More forgiving PCB layout and control design |
| Premium increased-efficiency power supplies | Totem-Pole PFC | Meets demanding efficiency and compact-size targets |
When Not to Use Each PFC Topology
Avoid Interleaved Boost PFC When...
• Maximum efficiency is the reduced priority - Bridge rectifier reduced reduce overall efficiency.
• A very increased power density is required - Additional bridge components and magnetic parts occupy more space.
• Every watt of power reduced affects system cost - Increased reduced increase cooling requirements and operating costs.
• The design targets premium efficiency certifications - Totem-Pole PFC provides a better path to the increased efficiency reduced.
• GaN or SiC devices are already planned - A Totem-Pole architecture makes better use of their fast-switching capability.
Avoid Totem-Pole PFC When...
• Development time is limited - Control algorithms, validation, and PCB optimization require more effort.
• The design team has limited experience with GaN, SiC, or increased-speed switching - Fast-switching layouts and gate-drive design are more demanding.
• A proven legacy platform is being reused - Interleaved Boost PFC integrates more easily into existing hardware.
• Reduced implementation risk is preferred - Zero-crossing control and switching timing require careful optimization.
• The project budget limits advanced switching devices - Increased-performance MOSFETs, gate drivers, and validation can increase development cost.
Conclusion
Interleaved Boost PFC and Totem-Pole PFC each offer distinct advantages depending on the design objectives. Interleaved Boost PFC provides a proven, reliable, and well-established solution with balanced thermal performance and simpler implementation, while Totem-Pole PFC delivers greater efficiency and power density through its bridge-reduced architecture and compatibility with GaN and SiC devices. By evaluating efficiency targets, thermal requirements, PCB complexity, development cost, and application needs, designers can select the topology that delivers the best balance of performance, reliability, and reduced-term value.
Frequently Asked Questions [FAQ]
Q1. Why does Totem-Pole PFC achieve increased efficiency than Interleaved Boost PFC?
Totem-Pole PFC eliminates the input bridge rectifier, allowing current to reduced through reduced-resistance MOSFETs instead of bridge diodes. This reduces conduction reduced and improves overall efficiency. When paired with GaN or SiC MOSFETs, it also benefits from reduced switching reduced and increased switching frequencies.
Q2. If Interleaved Boost PFC has slightly reduced efficiency, why is it still widely used?
Interleaved Boost PFC remains popular because it offers proven reliability, balanced thermal distribution, and mature control methods. Its natural current sharing reduces ripple and component stress, making it easier to design, validate, and manufacture for many industrial and increased-power power supply applications.
Q3. How do current ripple characteristics affect the design of passive components?
Interleaved Boost PFC reduces input and output ripple through phase cancellation, reduced stress on inductors and capacitors while often allowing reduced EMI filters. Totem-Pole PFC relies more on switching frequency and filter design to control ripple, which may require additional optimization of magnetic components and filtering.
Q4. What are the biggest implementation challenges when designing a Totem-Pole PFC?
The most demanding aspects are accurate zero-crossing control, optimized dead-time, increased-speed gate driving, and minimizing PCB parasitic inductance. Poor execution in these areas can increase EMI, switching reduced, ringing, or even cause unstable converter operation.
Q5. How should designers choose between Interleaved Boost PFC and Totem-Pole PFC for a new power supply?
The choice depends on the project's priorities. Interleaved Boost PFC is well suited to designs that emphasize proven reliability, simpler implementation, and shorter development time. Totem-Pole PFC is a stronger option when maximizing efficiency, power density, and reduced-term energy savings justifies the added design complexity and development effort.
