A decade counter is a digital counting circuit that cycles through ten states and then repeats the sequence. It forms an important part of many digital systems that require decimal counting or frequency division. This article explains the operating principle of decade counters, their internal structure, timing behavior, common IC implementations, and practical applications in electronic circuits.
Decade Counter Overview
A decade counter is a digital counter that counts through ten states, from 0 to 9, and then returns to 0 to repeat the sequence. Because it operates in ten states, it is also called a Mod-10 counter. In many circuits, a decade counter provides binary-coded decimal (BCD) output, where each decimal number is represented by four binary bits.
A decade counter is derived from a four-bit binary counter, which can normally represent sixteen states. Extra logic is added to limit the count to only the first ten states, so the counter resets after reaching the tenth state. This same principle can also be used to create other modulus counters that repeat after a selected number of states.
Decade Counter Operation
A decade counter advances through ten fixed binary states, with each clock pulse moving the count to the next state.
The sequence is:
0000 → 0001 → 0010 → 0011 → 0100 → 0101 → 0110 → 0111 → 1000 → 1001
After the tenth state, the counter returns to 0000 and the sequence repeats. The least significant bit changes on every clock pulse, while the higher-order bits change according to the binary counting pattern.
Truth Table of a Decade Counter
| Clock Pulse | QD | QC | QB | QA |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 |
| 6 | 0 | 1 | 1 | 0 |
| 7 | 0 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 |
The truth table shows how the four output bits represent decimal values from 0 to 9 in binary-coded decimal form. QA is the least significant bit (LSB), so it changes on every clock pulse. Each row corresponds to the counter state after a clock pulse. After the count reaches 9, the counter returns to the initial state and the sequence begins again.
State Diagram of a Decade Counter
Each state corresponds to a four-bit output value, and arrows show the transition that occurs after each clock pulse. The diagram visually confirms that the counter cycles through ten states before returning to the starting point.
Decade Counter Circuit Diagram
A decade counter circuit can be built from four flip-flops connected to form a binary counting structure. Additional logic is included to restrict the count to ten states.
The circuit detects the binary value 1010, which corresponds to decimal 10. When this state appears, a NAND gate generates a LOW signal that activates the clear inputs of the flip-flops. This signal resets all outputs to 0000, preventing the counter from continuing to the remaining binary states.
Because the reset occurs immediately after the tenth state appears, the counter repeatedly cycles through only ten states. Depending on the design, different flip-flop types such as JK, D, or T flip-flops may be used.
Timing Diagram of a Decade Counter
A timing diagram shows how the counter outputs change with each clock pulse. As the count advances from 0 to 9, QA changes on every pulse, while the higher-order bits change less often according to the binary counting sequence. The output pattern repeats every ten clock pulses, which allows the decade counter to function as a divide-by-10 circuit.
74LS90 Decade Counter IC
The 74LS90 is a widely used decade counter IC designed for divide-by-10 counting. It contains the internal flip-flops and logic needed to count from 0 to 9 and then return to 0. The chip provides four outputs QA, QB, QC, and QD which represent the count in binary-coded decimal (BCD) form. When the count reaches 10, the internal reset action clears the outputs back to 0000. The 74LS90 also has reset inputs that can be used for clearing the count or setting specific counter conditions. Multiple 74LS90 chips can be connected together to create larger counting circuits.
Binary Counter vs Decade Counter
| Feature | Binary Counter | Decade Counter |
|---|---|---|
| Counting Range | 0 to 2ⁿ − 1 | 0 to 9 |
| Modulus | Power of two | Mod-10 |
| Output Format | Binary | BCD |
| Reset Condition | After max state | After 1001 |
| Common Use | General counting | Decimal displays |
Cascading Decade Counters
A single decade counter can count only from 0 to 9. For larger counting ranges, two or more decade counters are connected in series, or cascaded. In this arrangement, the first counter handles the units digit, the second handles the tens digit, and the third handles the hundreds digit. This makes it possible to count ranges such as 00 to 99 or 000 to 999. Cascaded decade counters are widely used in circuits that need higher counting capacity, such as digital clocks, event counters, measurement instruments, and frequency meters.
Applications of Decade Counters
• Digital clocks and timers – Counters track seconds, minutes, and hours in timekeeping systems.
• Frequency division circuits – A decade counter divides the input frequency by ten, which helps generate lower-frequency clock signals for digital systems.
• Frequency measurement instruments – In frequency counters, the input signal is applied to the counter while a gate pulse allows counting for a fixed time interval. The number of pulses counted during this period represents the signal frequency.
• Digital display systems – Decade counters work with BCD decoders and seven-segment displays in calculators, meters, and digital counters.
• Event counting systems – Used in production monitoring, testing equipment, and data acquisition systems to record the number of events or pulses.
Conclusion
Decade counters provide a controlled ten-state counting sequence that fits naturally with decimal-based digital systems. By combining flip-flops with reset logic, they limit the count to values from 0 to 9 and repeat the cycle. Their clear structure, compatibility with BCD outputs, and ability to cascade make them practical components in many digital counting and measurement circuits.
Frequently Asked Questions [FAQ]
How does a decade counter reset after reaching 9?
A decade counter resets through logic that detects the binary value representing decimal 10 (1010). When this state appears, a reset signal clears all flip-flops back to 0000. This automatic reset prevents the counter from entering the remaining states of a four-bit binary counter, limiting the sequence to ten counts.
What is the difference between a BCD counter and a decade counter?
A BCD counter outputs numbers using the binary-coded decimal format, where each decimal digit is represented by four bits. A decade counter is a type of BCD counter that counts from 0 to 9 and then resets. In practice, many decade counters are implemented specifically to produce BCD output.
Can a decade counter be used to divide frequencies other than by 10?
Yes. While a decade counter naturally divides a signal by ten, its outputs can be combined with external logic to create other division ratios. By resetting the counter at a chosen state before reaching 10, the circuit can operate as a different modulus counter such as divide-by-5 or divide-by-6.
What factors limit the maximum speed of a decade counter?
The maximum operating speed depends on the propagation delay of the flip-flops and logic gates inside the counter. In ripple counters, each stage triggers the next one sequentially, which adds delay. This cumulative delay restricts how fast the counter can respond to incoming clock pulses.
How are decade counters connected to seven-segment displays?
A decade counter produces a four-bit BCD output that represents numbers from 0 to 9. This output connects to a BCD-to-seven-segment decoder, which converts the binary value into the correct segment signals for the display. The display then shows the corresponding decimal digit.
